Optimization of SiGe interface properties with ozone oxidation and a stacked HfO₂/Al₂O₃ dielectric for a SiGe channel FinFET transistor

Abstract

In this paper, the optimization of SiGe interface property for SiGe channel FinFET transistor is explored in detail. First, an optimal low-temperature ozone oxidation at 300 ℃ for 30 min was confirmed based on the Al2O3/Si0.7Ge0.3 MOS capacitors. This is because that a higher oxidation temperature and a longer oxidation time could suppress the formation of GeOX in the interface layer (IL), and significantly improve interface state density (Dit). Moreover, compared with Al2O3 sample, HfO2 sample can obtain a thinner capacitance equivalent oxide thickness (CET), but it is more vulnerable to deterioration of Si0.7Ge0.3 interface property because the GeOX in the IL is more likely to diffuse into HfO2 layer. To further optimize the Dit and CET of Si0.7Ge0.3 MOS capacitor simultaneously, a stacked HfO2/Al2O3 dielectric is proposed. Compared with the HfO2 sample, its frequency dispersions characteristics and Dit have been improved significantly since the thin Al2O3 layer prevents the diffusion of GeOX to HfO2 layer and controls the growth of GeOX. Therefore, a high quality Si0.7Ge0.3 interface property optimization technology is realized by development of a low-temperature ozone oxidation (300 ℃, 30 min) combined with a stacked HfO2/Al2O3 dielectric. In addition, a Si0.7Ge0.3 FinFET utilizing this newly developed interface property optimization scheme is successfully prepared. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 is obtained. The above result proves that these newly developed interface property optimization scheme is a practical technology for high mobility SiGe FinFET.

Si0.5Ge0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

“…This channel passivation process 3 × 10 13 eV −1 cm −2 to 5.1 × 10 12 eV −1 cm −2 was realized. 22 Therefore, it was directly applied to Si 0.5 Ge 0.5 channel. Figures 8a and 8b show the I DS -V GS and I DS -V DS curves of this optimized Si 0.5 Ge 0.5 channel FinFET, respectively.…”

The study of interface quality in HfO2/Si films probed by second harmonic generation

“…To accommodate the miniaturization of field-effect transistors (FETs), the high-k gate oxides have been developed recently, including hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), and alumina (Al 2 O 3 ) [1,2]. Among the potential candidates, HfO 2 becomes a leading material due to its superior high-k gate dielectric characteristics.…”

Ultrathin Al2O3 interfacial layer for Hf0.5Zr0.5O2-based ferroelectric field-effect transistors

“…In this study, we implemented an Al 2 O 3 IL between a ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) film and Si substrate through consecutive atomic layer deposition (ALD) processes without vacuum breaks. It is well known that Al 2 O 3 exhibits a better interfacial quality than those of the HfO 2 and ZrO 2 films directly deposited on various semiconductor surfaces, including Si, SiGe, and III-V compound substrates [10][11][12]. Therefore, it is reasonable to expect that the introduction of an Al 2 O 3 layer between the HZO film and Si substrate can lower the initial interface trap density and effectively suppress trap generation during P/E cycles.…”