2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST) 2021
DOI: 10.1109/mocast52088.2021.9493414
|View full text |Cite
|
Sign up to set email alerts
|

A novel time register with process and temperature calibration

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
4
2

Relationship

1
5

Authors

Journals

citations
Cited by 8 publications
(2 citation statements)
references
References 9 publications
0
2
0
Order By: Relevance
“…In the following section, the performance of the proposed circuits is presented. All circuits are designed and verified by simulation in Samsung 28 nm FD-SOI CMOS technology with a supply voltage V DD = 1 V. The voltage triple point of comparator was adjusted to be 0.5 V using an appropriate triple-point compensation circuitry [15]. Considering that the input pulse width T in is varied as a sinusoid, the maximum allowable peak-to-peak amplitude T in.pp.aval can theoretically be equal to T CLK , which is equal to 50 ns in our implementation.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…In the following section, the performance of the proposed circuits is presented. All circuits are designed and verified by simulation in Samsung 28 nm FD-SOI CMOS technology with a supply voltage V DD = 1 V. The voltage triple point of comparator was adjusted to be 0.5 V using an appropriate triple-point compensation circuitry [15]. Considering that the input pulse width T in is varied as a sinusoid, the maximum allowable peak-to-peak amplitude T in.pp.aval can theoretically be equal to T CLK , which is equal to 50 ns in our implementation.…”
Section: Resultsmentioning
confidence: 99%
“…Our work proposes the implementation of a 3rd order sampled-data low pass timemode FIR filter which is based on the novel time-mode multiplier and time-mode adder. Both circuits are based on the modification of a simple time register topology [15,16]. A 3rd order low-pass topology offers a satisfactory trade off between high-frequency rejection, chip area and current consumption.…”
Section: Introductionmentioning
confidence: 99%