A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip

Latif, Khalid; Rahmani, Amir-Mohammad; Nigussie, Ethiopia; Tenhunen, Hannu; Seceleanu, Tiberiu

doi:10.1109/dft.2011.16

Cited by 4 publications

(4 citation statements)

References 22 publications

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“…It can also solve various NoC issues such as fault, contention or deadlock. Latif et al proposed a partial virtual-channel sharing NoC architecture that reduces the impact of faults on system performance [6]. If one virtual-channel is faulty then only the corresponding buffers are affected and the rest of the resources Arbiter Fig.…”

Section: Related Workmentioning

confidence: 99%

“…Power consumption of matrix crossbar‫ן‬ I (6) where I is the number of input ports of crossbar Moreover, Figure 5 shows that the size of the crossbar is proportional to the square of flit size. Therefore, the area and power of crossbar switch is proportional to the square of flit size f. These relations are given in equation (7).…”

Section: Area Of Matrix Crossbar ‫ן‬ I (5)mentioning

confidence: 99%

“…However, this improvement in performance and contention happens at the expense of NoC chip area and power consumption. As depicted in Figure 1, implementing virtual channels needs at least to add extra resources to the router such as FIFO buffer for each VC, Demultiplexers and Multiplexers and VC allocator [1,3,4,5,6]. In this paper, we propose a new methodology and architecture for VC design that not only improves performance but also saves area and power.…”

Section: Introductionmentioning

confidence: 98%

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A Novel Virtual Channel Implementation Technique for Multi-core On-chip Communication

Gharan

Khan

2012

2012 Third Workshop on Applications for Multi-Core Architecture

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In this paper, a new approach for implementing virtual channels (VC) for multi-core interconnection networks is presented. In this approach, the flits of different packets interleave in a channel with a single buffer of nominal depth by using a rotating flit-by-flit arbitration. The routing path of each flit is guaranteed because the flits belonging to the same packet are attached with an ID tag at each router so that they are differentiable at downstream routers. We present this on-chip communication of packets through sharing of channel and buffer, which is a novel method of virtual channel implementation. Furthermore, we demonstrate it by adding arbitrary virtual channels depending on the number of packet requests for a physical channel. In this way, NoC (Network-on-Chip) contention can be removed cheaply. Moreover, we discuss contention free communication where the depth of shared buffer does not affect the performance. A contention-free communication with small (one) buffer depth can create an efficient on-chip communication with high performance, small chip area and low power consumption.

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Section: Related Workmentioning

confidence: 99%

Section: Area Of Matrix Crossbar ‫ן‬ I (5)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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A Novel Virtual Channel Implementation Technique for Multi-core On-chip Communication

Gharan

Khan

2012

2012 Third Workshop on Applications for Multi-Core Architecture

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“…FIFO buffer for each VC, De-multiplexers and Multiplexers for each input-port as well as VC allocator and bigger switch allocator for the arbiter[1,9,10,11,12].…”

mentioning

confidence: 99%

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

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The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

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Statically adaptive multi FIFO buffer architecture for network on chip

Oveis-Gharan

Khan

2015

Microprocessors and Microsystems

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A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip

Cited by 4 publications

References 22 publications

A Novel Virtual Channel Implementation Technique for Multi-core On-chip Communication

A Novel Virtual Channel Implementation Technique for Multi-core On-chip Communication

Virtual channel organization and arbitration for network on chip router architecure

Statically adaptive multi FIFO buffer architecture for network on chip

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