A Novel Virtual Channel Implementation Technique for Multi-core On-chip Communication

Gharan, Masoud Oveis; Khan, Gul N.

doi:10.1109/wamca.2012.12

Cited by 9 publications

(3 citation statements)

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“…Their link-list approach is expensive in terms of hardware, but provides better communication performance [7]. We also explored the use of DAMQ buffer by implementing miniature dynamic VCs, namely, shared buffer VCs (SBVCs) [13]. The SBVC investigation was mainly conducted to investigate the effect of varying the number of VCs of a channel and their buffer depth on the overall NoC throughput.…”

Section: Previous Research Workmentioning

confidence: 99%

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Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Oveis-Gharan

Khan

2016

IEEE Trans. VLSI Syst.

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The number of cores on a chip is rapidly increased the on chip need an efficient communication structure as network on chip (NoC). The channel buffer organization of NoC uses virtual channels (VCs) to improve data flow and performance of the NoC system. Dynamically allocated multi queues are an good mechanism to reach VC flow control with maximum no of buffer utilization. In this design, VCs employ variable number of buffer slots depending on the network traffic. we propose a new input port micro architecture to cooperate our efficient dynamic VC (EDVC) approach that is built on DAMQ buffers. To show the advantages of EDVC, we compare its micro-architecture with that of the traditional dynamic VC (CDVC), it's also employs link-list tables for buffer organization. In terms an hardware, EDVC input-port organization consumes on average 51% less power for ASIC design when compared with the CDVC input port. The saving is even good when compared with VC regulator methodology. This EDVC approach can improve NoC latency by 38%-48% and throughput by 100% on average as compared with the CDVC mechanism. The proposed design parameters are analyzed using Xilinx 9.1.

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Section: Previous Research Workmentioning

confidence: 99%

“…The VC mechanism for wormhole routing is a common approach used in many NoC designs [10], [13], [15]. In some situations, VC can contain two parts of two packets at a time.…”

Section: Novelty Of Edvc Mechanismmentioning

confidence: 99%

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

Oveis-Gharan

Khan

2016

IEEE Trans. VLSI Syst.

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“…However, this still relies on input buffers. The improvement of the congestion of incoming packets can be also checked by the virtual channel (VC) scheme as presented in work [26,27]. Virtual channel scheme multiplexes a physical channel using virtual channels (VCs), leading the reduction in latency and increase in network throughput.…”

Section: Related Workmentioning

confidence: 99%

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

Nazir¹,

Mir²

2016

IJCNIS

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Abstract-The communication between processing elements is suffering challenges due to power, area and latency. Temporary flit storage during communication consumes the maximum power of the whole power consumption of the chip. The majority of current NoCs consume a high amount of power and area for router buffers only. Removing buffers and virtual channels (VCs) significantly simplifies router design and reduces the power dissipation by a considerable amount. The buffering scheme used in virtual channeling in a networkon-chip based router plays a significant role in determining the performance of the whole network-onchip based mesh. Elastic buffer (EB) flow control is a simple control logic in the channels to use pipeline flipflops (FFs) as storage locations. With the use of elastic buffers, input buffers are no longer required hence leading to a simplified router design. In this paper properties of buffers are studied with a test microarchitecture router for several packet injection rates given at an input port. The prime contribution of this article is the evaluation of various forms of the elastic buffers for throughput, FPGA resource utilization, average power consumed, and the maximum speed offered. The article also gives a comparison with some available buffering policies against throughput. The paper presents the synthesis and implementation on FPGA platforms. The work will help NoC designers in suitable simple router implementation for their FPGA design. The implementation targets Virtex5 FPGA and Stratix III device family.

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