A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

Abstract

In view of device scaling issues, embedded DRAM (eDRAM)\ud technology is being considered as a strong alternative to conventional\ud SRAM for use in on-chip memories. Memory cells designed using eDRAM\ud technology in addition to being logic-compatible, are variation tolerant\ud and immune to noise present at low supply voltages. However, two major\ud causes of concern are the data retention capability which is worsened by\ud parameter variations leading to frequent data refreshes (resulting in large\ud dynamic power overhead) and the transient reduction of stored charge\ud increasing soft-error (SE) susceptibility. In this paper, we present a novel\ud variation-tolerant 4T-DRAM cell whose power consumption is 20.4%\ud lower when compared to a similar sized eDRAM cell. The retention time\ud on-average is improved by 2.04X while incurring a delay overhead of\ud 3% on the read-access time. Most importantly, using a soft-error (SE)\ud rate analysis tool, we have confirmed that the cell sensitivity to SEs is\ud reduced by 56% on-average in a natural working environmentPeer ReviewedPostprint (published version

New 4T-based DRAM cell designs

“…Although this phenomenon (referred as to drain induced barrier lowering, or DIBL) has been extensively investigated in the past [13][14][15], the leakage problem has become a prominent cause of high power consumption for CMOS technology at nano scaled feature sizes. New schemes such as those utilizing the provision of a gated diode in a 3T1D cell [1], have been proposed to mitigate the above problems for designing a reliable, low power and high retention DRAM cell. The addition of transistors also contributes to a better tolerance to a Single-Event Upset (SEU) [16,17].…”

“…While in today's microprocessors, on-chip memory occupies a significant portion of the overall die area; it is extensively used to provide high system performance, while considering low power requirements [1,2]. Dynamic memories have been extensively used for data storage structures in the processor core due to the transient nature of the data flow.…”

“…The techniques of gated diode and forward body-biasing are then applied by utilizing schemes that improve over the circuits of [1] in most figures of merit for performance. The operations of the proposed DRAM cells are analyzed, simulated and compared in detail using HSPICE tool.…”

“…Dynamic memories have been extensively used for data storage structures in the processor core due to the transient nature of the data flow. Different designs of a Dynamic Random-Access Memory (DRAM) cell have been proposed; among them, the 3T1D DRAM cell [1] is a promising scheme due to the small area, the nondestructive read process and the good retention time. However, the operation of this cell is heavily influenced by process fluctuations [3][4][5] and external induced phenomena.…”

Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis

“…The eDRAM cell's retention time is defined as the interval between refresh operations at which an eDRAM cell can retain a reliable bit state [9] [10]. As the feature size continues to decrease, the eDRAM cell size reduction imposes challenges to eDRAM design by decreasing the retention time of eDRAM cell, but also leads to reduced reliability in terms of increasing the susceptibility of eDRAM cell to the soft errors [11] [12] [13] [14].…”