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ISBN: 0769518311This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach

In view of device scaling issues, embedded DRAM (eDRAM)\ud technology is being considered as a strong alternative to conventional\ud SRAM for use in on-chip memories. Memory cells designed using eDRAM\ud technology in addition to being logic-compatible, are variation tolerant\ud and immune to noise present at low supply voltages. However, two major\ud causes of concern are the data retention capability which is worsened by\ud parameter variations leading to frequent data refreshes (resulting in large\ud dynamic power overhead) and the transient reduction of stored charge\ud increasing soft-error (SE) susceptibility. In this paper, we present a novel\ud variation-tolerant 4T-DRAM cell whose power consumption is 20.4%\ud lower when compared to a similar sized eDRAM cell. The retention time\ud on-average is improved by 2.04X while incurring a delay overhead of\ud 3% on the read-access time. Most importantly, using a soft-error (SE)\ud rate analysis tool, we have confirmed that the cell sensitivity to SEs is\ud reduced by 56% on-average in a natural working environmentPeer ReviewedPostprint (published version

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