Evaluation of a soft error tolerance technique based on time and/or space redundancy

Anghel, Lorena; Alexandrescu, Dan; Nicolaidis, M.

doi:10.1109/sbcci.2000.876036

Cited by 74 publications

(33 citation statements)

References 17 publications

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“…D etectin g rransienc upsets in rh e co mbinar ionallogic is m uch mo re COI11 -pl ex beca use ir requi res evaluat io n of rhe inrensiry of rh e pu lse ge nerared by the charged-parricl e srr ike. Prev io lls work proposed logic duplicarion, time red undan cy, and ex tra rran sistors for SET derecrio n. 6 These methods requi re cos dy design modificati on. Our method uses BICS connec[ed to rhe bulk of th e transistors; rhis redu ces area, performance, and power d issipa rion penalries whi le increas ing rh e effi ciency of derecting SEUs and SETs in inregrared circuirs.…”

Section: Set)3 Formentioning

confidence: 99%

Using Bulk Built-in Current Sensors to Detect Soft Errors

et al. 2006

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Variaus e nergeric particles in rh e space radia~ (íon environmenr C. 1.11 inreracr with silicon (Q cause undcsirable effects. When a single heavy ion strikes sili col1, ir loses irs energy by crea rin g frc e elcc rro n-hole pairs, resu]r ing in a dense ionized rrack in the local region. Protons and neurrons can cause nuclear imcracrions wh en pass ing through rhe material. The rccail a150 prod uces ionizar ian , which generates a tran sic nt current pulse (har can cau se an upset wh en ilHe rprered as a signal in eh e circuic. With technology sca ling imo deepsubmi cron dimens ions, the efreccs of energetic particle h its become a co nce rn even at sea levei, wh ere rhe major hi gh-e nergy radiarion source is atmospheric neurrons and prorons.A singlc partide can hit eirh er the sequentiaJ logic ar rhe combinarionallogic in th e silicon. When an energetic partide strikes one of a memory cell 's sens itive sires, the effect ca n produce an inversion in th e srored value-in oeher words, a bit Aip in rhe memory ceU. This is called a single-evem upset (SEU) .2 Whe n an energeri c particle hits a se nsitive site in rhe com bi national logic block, ir also generates a rransiem currem pulse. This phenomenon is called a single-evem rran sieIH (SET).3 ForPublished by the IEEE Computer Society combinational logi c bloc ks with reg istered outputs, the SET can evemually appear at rh e inpur of th e Aip-Aops placed at the com b inationallogic ourpurs, u nless t he induced rransie m pulse is e it he r 10gica1l y or electricall y masked by t he logic inpurs. If interpreted as a valid signal in che register inpU[, rhi s SET ca n cause an in co rrect valu e to be srored in th e register, provoking a soft crro r.Conrinuous rechno logy evo lu ri o n and small e r rransiswr featu res have made so ft errors on dev ices more frequ ento D etecein g soft e rrors in combinarional a nd sequentia l logic is criti cai for avoiding erro rs in the c ircuir applicarion. Howeve r, t his eas k is co mplex becau se the intern a i ci rcu ir signals a re decrcasing to che same order of magni tud e as the transienr currenrs,generated by cha rgedpartide strikes.Researchers have proposed a bu ilr-in currem senso r (BIC S) connected to t he powe r lines for moniroring on-chip current variati ons provoked by pcrmanent faules, such as stu ckar fallles, a nd by soft erro rs in memoryelements.-4,5 However, to rh e besr of our knowledge. no one has yer proposed a BI CSbased method for derecring SETs in combinafional lo gic, a nd (his iss ue is gain ing importance in new rechn ologies. We propose an approach for using BI CS to derect transiem

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Section: Set)3 Formentioning

confidence: 99%

Using Bulk Built-in Current Sensors to Detect Soft Errors

et al. 2006

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“…The use of time and hardware redundancy has already been proposed in the past [13,14,15] for the detection of transient upsets and upset tolerance. The goal is to take advantage of the transient pulse characteristic to compare signals at two different moments.…”

Section: Time and Hardware Redundancy For Asicsmentioning

confidence: 99%

Reducing pin and area overhead in fault-tolerant FPGA-based designs

Lima¹,

Carro²,

Reis³

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications. However, TMR comes with high area and power dissipation penalties. The proposed technique was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. We present some fault coverage results and a comparison with the TMR approach.

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“…Usually, the techniques employed to add fault tolerance to electronic systems are based on hardware and/or time redundancy [5][6][7]. Among these techniques the most popular is the Triple Modular Redundancy (TMR), which consists in triplicating the designed circuit, and delivering the system copies outputs to a majority voter.…”

Section: Introductionmentioning

confidence: 99%

“…Among these techniques the most popular is the Triple Modular Redundancy (TMR), which consists in triplicating the designed circuit, and delivering the system copies outputs to a majority voter. If there is an error in one of the blocks, two of them continue to operating properly and the correct value is chosen by the voter [7][8][9].…”

Section: Introductionmentioning

confidence: 99%