A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics

Hosseini, Seied Ali; Etezadi, Sajjad

doi:10.1007/s00034-019-01158-2

Cited by 24 publications

(8 citation statements)

References 29 publications

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“…The simulation was performed using HSPICE software and 32nm CNTFET library. In a reported work by Hosseini and Etezadi [4], a novel ternary MVL comparator was introduced that is expandable to a quaternary one. Using CNTFET, the reported MVL comparator was designed and simulated in both ternary and quaternary modes.…”

Section: Related Workmentioning

confidence: 99%

A New Multi-Valued Logic Buffer and Inverter Using MOSFET Based Differential Amplifier

Mokhtari

Kabiri

2022

IJE

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The aim of this work is to assist the design of decenary Multi-Valued Logic (MVL) circuits. This paper reports a work, in which, analog voltage-based circuitry is used to design MVL circuits. In this paper, some analog circuits are reported as elements that can be used in Multi-Valued Logic (MVL) circuitry. This article reported a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)-Based Differential Amplifier (MBDA) as a key element in designing decenary MVL arithmetic unit. Operating voltage range and linearity of the gain are two important characteristics of this element. The operating voltage range for the MBDA is 0V to 5.5V as a output voltage.The achieved linear gain is within the range of 0.1V to 5.3V. Analog inverter and correction buffer circuits are reported based on MBDA. Analog inverter will be used in computational and logical decenary MVL circuits. The correction buffer is designed as an element to eliminate noises and signal drift at the output of the MVL gates and throughout data transfer.

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Section: Related Workmentioning

confidence: 99%

A New Multi-Valued Logic Buffer and Inverter Using MOSFET Based Differential Amplifier

Mokhtari

Kabiri

2022

IJE

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“…Consequently, transistor channels can be constructed of the SWCNT type instead of bulk silicon, which is used in traditional CMOS transistors. By positioning the CNT as a channel in the field-effect transistor, a new device is devised, generally known as CNTFET [10] or tube-FET [9].…”

Section: Cntfet Technology and Mvl Circuits Review A Carbon Nanomentioning

confidence: 99%

“…where, V π is a constant parameter which determines the carbon π -π bound energy in tight bonding with a value of 3.033 eV and e is the electron charge [10]; the V th has an inverse relation with tube diameter and varies with the tube diameter derived from n 1 and n 2 . This feature, together with other advantages of CNTFETs such as fine pitch and excellent device characteristics, makes them promising candidates for replacing silicon CMOS transistors.…”

Section: Cntfet Technology and Mvl Circuits Review A Carbon Nanomentioning

confidence: 99%

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

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The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

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“…Compared with the binary logic that has been maturely applied in the electronics field, multivalued logic with stronger single-line information-carrying ability can not only effectively reduce the number of wires and chip area, but also have stronger calculation potential and lower manufacturing costs. [9][10][11] Three is the smallest radix in multivalued logic. Research on ternary logic circuits is the least difficult and is easy to make a breakthrough compared with other multivalued logic circuits with a higher radix, therefore, it has become an important research direction in the field of integrated circuit design.…”

Section: Introductionmentioning

confidence: 99%

Delay optimization for ternary fixed polarity Reed–Muller circuits based on multilevel adaptive quantum genetic algorithm

Xiaoqian

Wang

et al. 2021

Int J Intell Syst

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Delay optimization has now emerged as an important optimization goal in logic synthesis. The delay optimization for ternary fixed polarity Reed-Muller (FPRM) circuits aims to find a ternary FPRM circuit with a minimum delay. Because the delay optimization for ternary FPRM circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive quantum genetic algorithm (MAQGA), which divides individuals into three-level populations: high-level population, intermediate-level population, and low-level population and uses the proposed ternary quantum rotation gate, proposed ternary quantum correction gate, and proposed multi-operator adaptive mutation mechanism to make the three-level populations evolve. Moreover, based on the proposed delay decomposition strategy, we propose a delay optimization approach (DOA) for ternary FPRM circuits under the unit delay model, which searches for a ternary FPRM circuit with a minimum delay using the MAQGA. Experimental results demonstrated the effectiveness and superiority of the DOA in optimizing the delay of ternary FPRM circuits.

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A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics

Cited by 24 publications

References 29 publications

A New Multi-Valued Logic Buffer and Inverter Using MOSFET Based Differential Amplifier

A New Multi-Valued Logic Buffer and Inverter Using MOSFET Based Differential Amplifier

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

Delay optimization for ternary fixed polarity Reed–Muller circuits based on multilevel adaptive quantum genetic algorithm

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