A New Multi-Valued Logic Buffer and Inverter Using MOSFET Based Differential Amplifier

Abstract

The aim of this work is to assist the design of decenary Multi-Valued Logic (MVL) circuits. This paper reports a work, in which, analog voltage-based circuitry is used to design MVL circuits. In this paper, some analog circuits are reported as elements that can be used in Multi-Valued Logic (MVL) circuitry. This article reported a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)-Based Differential Amplifier (MBDA) as a key element in designing decenary MVL arithmetic unit. Operating voltage range and linearity of the gain are two important characteristics of this element. The operating voltage range for the MBDA is 0V to 5.5V as a output voltage.The achieved linear gain is within the range of 0.1V to 5.3V. Analog inverter and correction buffer circuits are reported based on MBDA. Analog inverter will be used in computational and logical decenary MVL circuits. The correction buffer is designed as an element to eliminate noises and signal drift at the output of the MVL gates and throughout data transfer.

Prototype design and modeling of active-loaded differential amplifier using Double-Gate MOSFET

“…Investigating various differential amplifier topologies, the gain of a balanced differential amplifier for a 50 Ω input was much higher than the gain of a fully-differential amplifier, where the minimum gain of the balanced topology was measured at 39 dB, and the maximum gain of the fully-differential topology was approximately 35 dB for a bandwidth of 1.3 GHz. Kabiri and Mokhtari [11] have used a differential amplifier to design Multi-Varied Logic (MVL) circuits, where the differential amplifier built uses a supply voltage of 0-5.5 V, as a dual-supply is used to improve the development of digital devices. Jain et al [12] have implemented a two-stage differential amplifier using stacked transistors for bio-medical applications.…”

Design and Performance Analysis of 6H-SiC Metal-Semiconductor Field-Effect Transistor with Undoped and Recessed Area under Gate in 10nm Technology

“…By eliminating dopants from the gate region, ionized impurity scattering is reduced, resulting in higher electron mobility and improved carrier concentration. Furthermore, the recessed gate architecture provides precise control over the gate-to-channel distance, mitigating short-channel effects and enhancing gate control over throughout the channel [8].…”