A One-Cycle Asynchronous FIFO Queue Buffer Circuit

Abdel-Hafeez, Saleh; Quwaider, Muhannad

doi:10.1109/icics49469.2020.239548

Cited by 6 publications

(5 citation statements)

References 14 publications

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“…We implement and test the datapath unit of size 64‐row × 64‐bit using SRAM 8T‐Cells, which is a common FIFO size in many chips 1–4,7,8 . Additionally, two control units, one with synchronous and the other with asynchronous circuitry, are implemented and integrated with datapath unit for testing purposes.…”

Section: Results and Comparison Analysismentioning

confidence: 99%

“…An additionally advantage factor is that the datapath processes write and read operations without any latencies, which is usually implemented as brute‐force, cascaded DFFs in other designs 4–20 to synchronize the incoming data with the internal clock. Thus, the datapath exploits high overall performance and processes data on every cycle (i.e., every two nonoverlapping signals process new data).…”

Section: Results and Comparison Analysismentioning

confidence: 99%

“…In order to flip a FIFO's operation between synchronous and asynchronous, an entirely new circuit design is required, which leaves little design flexibility. In this work, we extend prior work on FIFO design 1,8 and present a flexible, reconfigurable FIFO that can be easily flipped between synchronous and asynchronous. The datapath remains the same for both synchronous and asynchronous operation using an arbitrarily sized SRAM‐based memory with two separate read and write ports, while the control unit activates different signals based on the operation configuration (i.e., synchronous or asynchronous).…”

Section: Introductionmentioning

confidence: 95%

“…These FIFOs usually orchestrate communication between components that may be using different fabrication technology. Many asynchronous FIFOs play a major role in the Internet of Things (IoT) 8 and communication devices such as routers, Networks on Chip (NoCs) 9 globally asynchronous locally synchronous (GALS) networks, etc 10,11 …”

Section: Introductionmentioning

confidence: 99%

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Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Abdel‐hafeez

Gordon‐Ross

2021

Circuit Theory & Apps

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We present a new FIFO (first‐in first‐out) architecture for both synchronous and asynchronous communication for high‐speed and low‐power operation. Our FIFO design is reconfigurable and scalable using a separate datapath with an 8T‐Cell SRAM and control circuits, which enables specialization for different application requirements. The datapath uses a two‐phase clock system of nonoverlapping signals such that one signal increments the address pointer, while the other signal activates the memory decoder for data reading and writing. This structure halves the critical path delay and simplifies the timing operations between the memory decoder and address pointer while maintaining robustness against process‐voltage‐temperature (PVT) variations. Our design uses two alternative control circuits to manage separate synchronous and asynchronous operations by generating nonoverlapping control signals that drive the datapath circuit. The empty‐full flag circuitry records only the state of the address pointers' rollover independent of the memory size, and, thus, improves scalability and reconfigurability. Compared to prior works, our design is 5X faster with a 2.3X lower power consumption and has a throughput of 1 Giga‐Word/s. For a 64‐bit word size with a free latency cycle. Additionally, our design functions clocklessly with the synthesizable structure for asynchronous communication that leverages Internet of Things (IoT) and Networks on Chip (NoCs) applications.

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Section: Results and Comparison Analysismentioning

confidence: 99%

Section: Results and Comparison Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Abdel‐hafeez

Gordon‐Ross

2021

Circuit Theory & Apps

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“…With the continuous development of integrated circuit technology, the size of integrated circuit devices is gradually reduced, and the direction of integrated circuit design is changed from integrating more devices or chips to integrating more functions on a single chip. SoC (System integrated chip) technology is thus born on the basis of ASIC and has achieved rapid development [1]. With its characteristics of low energy consumption, fast speed, small size and rich functions, it has gradually become a mainstream design method in the fields of communication, computer, consumer electronics and so on.…”

Section: Introductionmentioning

confidence: 99%

Design and optimization of asynchronous FIFO based on Verilog HDL

Cheng

2023

Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022)

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SoC system is a new chip design scheme, which can integrate a large number of functions in the same chip, so it has high requirements for asynchronous data transmission between different modules. Asynchronous FIFO is an efficient and reliable data transmission mode, which is often used as a data matcher in SoC system. This paper, through the modular design, layer by layer construction method, designs a asynchronous FIFO, and for the common problems to optimize, makes its performance more reliable. And according to the simulation results, it can be judged that this design can effectively and reliably carry out asynchronous data transmission.

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