A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs

Fan, Yibo; Huang, Leilei; Bai, Yufeng; Zeng, Xiaoyang

doi:10.1109/tcsii.2015.2468915

Cited by 8 publications

(3 citation statements)

References 19 publications

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“…Although this design can lead to higher throughput, there are many difficulties in reading and writing data. In response to this, Fan et al [21] proposed a parallel-access storage processing method, which provides an effective data access method for DCT and solves the storage difficulties caused by multiple TU sizes.…”

Section: A Limitation Of Idct Output Formatmentioning

confidence: 99%

A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder

2019

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In the High Efficiency Video Coding (HEVC), a variety of CU sizes and intra prediction modes significantly improve coding efficiency, but also bring higher computational complexity. This paper proposes a new compact VLSI architecture for HEVC intra prediction, which is geared towards 8K video decoding. It supports all the transform unit (TU) sizes and 35 HEVC intra prediction modes. First, this paper introduces a TU-oriented intra predictor with a throughput of 32 pixels, which can be newly arranged with the TU size. It can be a line of 32 pixels, two lines of 16 pixels, 4 lines of 8 pixels or four lines of four pixels. This TU-oriented architecture allows intra-prediction and inverse discrete cosine transform (IDCT) to be computed in parallel, removing the memory between them. In addition, a horizontal and vertical line buffer for reference sample is proposed, which only cost 0.8K bit and is implemented by register files with SRAM-free. Finally, to further reduce hardware consumption, multipliers can be shared in the prediction. The implementation result shows that the compact architecture supports 8K video application and costs 66.2K logic gates, which is synthesized with the TSMC 65nm process under 400MHz. INDEX TERMS 32-pixel, TU-oriented, SRAM-free, HEVC intra prediction, 8K decoder.

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Section: A Limitation Of Idct Output Formatmentioning

confidence: 99%

A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder

2019

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“…The architecture still consumes large circuit area. Several works present low-cost transpose architecture to deal with the area overhead [14][15][16][17][18]. The multiplexer is used to control the 1-D inverse discrete cosine transform (IDCT) core for the calculation of 1-D and 2-D operations, and the 1-D IDCT core uses matrix decomposition to reduce the required circuit area.…”

Section: Introductionmentioning

confidence: 99%

“…Besides, the transform size can be up to 32 × 32 in HEVC standard; thus, the transpose memory consumes large of circuit area. Several works present low-cost transpose architecture to deal with the area overhead [14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

High‐throughput IDCT architecture for high‐efficiency video coding (HEVC)

Chen

2017

Circuit Theory & Apps

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This paper presents a hardware design capable of supporting high-efficiency video coding inverse discrete cosine transform (IDCT) with a 32 × 32 transform unit size, using a single 1-D IDCT core with transpose memory to reduce costs. The proposed 1-D IDCT core employs 16 computation paths for high throughput and is implemented using distributed arithmetic to facilitate the sharing of hardware resources. The proposed 1-D IDCT is capable of calculating 1-D and 2-D data simultaneously along 32 parallel paths. When implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS technology, the proposed 2-D transform core provides throughput of 6.4 gigapixels/s with a gate count of 335 k. The results show that a superior hardware efficiency can be achieved in the proposed 32-point IDCT core compared with the existing works.

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