A parallel decoder for low latency decoding of turbo product codes

Argon, C.; McLaughlin, S.W.

doi:10.1109/4234.984698

Cited by 36 publications

(18 citation statements)

References 5 publications

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“…Our scheme is similar to the parallel decoder presented in [2]. However, instead of the product turbo code, we apply the parallel algorithm to convolutional turbo code.…”

Section: Introductionmentioning

confidence: 97%

A Parallel Decoder Design for Low Latency Turbo Decoding

2007

Second International Conference on Innovative Computing, Informatio and Control (ICICIC 2007)

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To reduce the iterative decoding time in turbo coding, a new parallel decoding algorithm for turbo decoders is proposed. Different than the previous approaches of using multiple SISO decoders to process sub-block MAP decoding in parallel, the new parallel turbo decoder immediately passes the extrinsic information of each message bit which is generated by one SISO decoder to the other SISO decoders bit by bit. Thus, the component decoders corresponding to different received sequence perform in parallel and the interleaver delay is eliminated. Simulation results show that with this parallel scheme, decoding time is halved while the performance in terms of BER is comparable, and in some cases superior, to the general turbo decoder.

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“…Our scheme is similar to the parallel decoder presented in [2]. However, instead of the product turbo code, we apply the parallel algorithm to convolutional turbo code.…”

Section: Introductionmentioning

confidence: 97%

A Parallel Decoder Design for Low Latency Turbo Decoding

2007

Second International Conference on Innovative Computing, Informatio and Control (ICICIC 2007)

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“…It applies the Chase algorithm iteratively on the row and column decoding, but still in a serial fashion. In order to halve the decoding latency, a parallel TPC decoder has been proposed in [10]. As opposed to the conventional serial TPC decoder, the row and column decoders in this method operate in parallel and send each other the updated extrinsic information immediately after a row or column has been decoded.…”

Section: A Conventional Decoding Methods Of Tpcmentioning

confidence: 99%

Replica shuffled iterative decoding

Zhang

Wang

Fossorier

et al. 2005

Proceedings. International Symposium on Information Theory, 2005. ISIT 2005.

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Replica shuffled versions of interactive decoders of turbo codes, low-density parity-check codes and turbo product codes are presented. The proposed schemes converge faster than standard and previously proposed shuffled approaches. Simulations show that the new schedules offer good performance versus complexity/latency trade-offs. IEEE International Symposium on Information Theory (ISIT)This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of Mitsubishi Electric Research Laboratories, Inc.; an acknowledgment of the authors and individual contributions to the work; and all applicable portions of the copyright notice. Copying, reproduction, or republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Research Laboratories, Inc. All rights reserved. AbstractReplica shuffled versions of iterative decoders of turbo codes, low-density parity-check codes and turbo product codes are presented. The proposed schemes converge faster than standard and previously proposed "shuffled" approaches. Simulations show that the new schedules offer good performance versus complexity/latency trade-offs.This work may not be copied or reproduced in whole or in part for any commercial purpose. Permission to copy in whole or in part without payment of fee is granted for nonprofit educational and research purposes provided that all such whole or partial copies include the following: a notice that such copying is by permission of Mitsubishi Electric Research Laboratories, Inc.; an acknowledgment of the authors and individual contributions to the work; and all applicable portions of the copyright notice. Copying, reproduction, or republishing for any other purpose shall require a license with payment of fee to Mitsubishi Electric Research Laboratories, Inc. All rights reserved. Abstract-Replica shuffled versions of iterative decoders of turbo codes, low-density parity-check codes and turbo product codes are presented. The proposed schemes converge faster than standard and previously proposed "shuffled" approaches. Simulations show that the new schedules offer good performance versus complexity/latency trade-offs.

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“…Thus, other turbo decoding structures such as parallel decoding 2 , shuffled decoding 3 , and its variants 4 were proposed to shorten the decoding latency. In the parallel decoding, all component decoders operate simultaneously.…”

Section: Introductionmentioning

confidence: 99%

On the MAP-Level Delay Reduction of Turbo Decoding

Sun¹,

Shou²,

Chuan³

2013

Proceedings of the 2013 International Conference on Advanced Computer Science and Electronics Information

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-A time-offset scheme for the shuffled turbo decoding is proposed. The decoding latency of the proposed scheme is shorter than the serial turbo decoding by offsetting the decoding timing of two component decoders. Meanwhile, its BER performance is better than the shuffled turbo decoding. We found that the effective extrinsic information is the key for the BER performance. Simulation results show that our scheme can flexibly balance the decoding latency and BER performance.

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A parallel decoder for low latency decoding of turbo product codes

Cited by 36 publications

References 5 publications

A Parallel Decoder Design for Low Latency Turbo Decoding

A Parallel Decoder Design for Low Latency Turbo Decoding

Replica shuffled iterative decoding

On the MAP-Level Delay Reduction of Turbo Decoding

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