A parallel decoder of programmable Huffman codes

Wei, B.W.Y.; Meng, Tao

doi:10.1109/76.388067

Cited by 32 publications

(12 citation statements)

References 8 publications

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“…One can see that the second occurrence of the string CCABDE of length 6 is 9 characters away from its previous occurrence and is replaced by the couple (6,9). This method brings a compression rate of s c = 23.4% of the string.…”

Section: Description Of the Different Encoding Methodsmentioning

confidence: 97%

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FPGA-based architecture for hardware compression/decompression of wide format images

Akil

Perroton²,

Grandpierre³

2006

J Real-Time Image Proc

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Section: Description Of the Different Encoding Methodsmentioning

confidence: 97%

“…Using properties described in [5,6], the table of the ''minimum codes'' is computed. From this table, we deduce the length of the Huffman code to be decoded and for each code length the value V a = (Address_code_Min) -Code_Min is computed and inserted into the table ''Base memory''.…”

Section: Different Approaches To Decode the Compressed Datamentioning

confidence: 99%

FPGA-based architecture for hardware compression/decompression of wide format images

Akil

Perroton²,

Grandpierre³

2006

J Real-Time Image Proc

View full text Add to dashboard Cite

show abstract

“…Moreover, designs can be pipelined into stages of codeword length determination and finding the corresponding symbol since the length information is sufficient to extract a codeword [13]. Furthermore, the traditional pattern matching has been replaced with arithmetic operations utilizing the properties of codeword table, e.g., leading characters and numerical properties [14]- [16].…”

Section: B Parallel Decodersmentioning

confidence: 99%

Multiple-symbol parallel decoding for variable length codes

Nikara

Vassiliadis

Takala

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an -bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redundant number of codeword lengths from which incorrect values are removed by recursive selection. Next, the index for each symbol corresponding the detected codeword is generated from the length determining the page and the partial codeword defining the offset in symbol table. The symbol lookup can be performed independently from symbol table. Finally, the sum of the valid codeword lengths is provided to an external shifter aligning the encoded input stream for a new decoding cycle. In order to prove feasibility and determine the limiting factors of our proposal, the variable length decoder has been implemented on an field-programmable gate-array (FPGA) technology. When applied to MPEG-2 standard benchmark scenes, on average 4.8 codewords are decoded per cycle resulting in the throughput of 106 million symbols per second.

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“…It decodes multiple symbols (different from [2,3,6,8,9,10,13]) and exploits arbitrary codelength buffers and variable output rate (different from [1]- [4], [6]- [13]). Finally, we propose a specific hardware mechanism, which improves the cycle time of the decoder.…”

Section: Related Workmentioning

confidence: 99%

“…Moreover, designs can be pipelined into stages of codelength determination and finding the corresponding symbol since length information is sufficient to extract codeword [9]. Furthermore, the traditional pattern matching has been replaced with arithmetic operations utilizing the properties of codeword table, e.g., leading characters and numerical properties [10,11,13].…”

Section: Related Workmentioning

confidence: 99%

Parallel multiple-symbol variable-length decoding

Nikara

Vassiliadis

Takala

et al.

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

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In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N -bit buffer whose accumulated codelength is at most N . The proposed method partially breaks the recursive dependency related to the MPEG-2 VLD. All possible codewords in the buffer are detected in parallel and the sum of the codelengths is provided to the external shifter aligning the variable-length coded input stream for a new decoding cycle. Two length detection mechanisms are proposed: the first approach determines the length in a parallel/serial fashion and the second using a new device denoted as MultiplexedAdd. In order to prove feasibility and determine the limiting factors of our proposal, the parallel/serial codeword detector with 32-bit input has been described in behavioral non-optimized VHDL and mapped onto Altera' s ACEX EP1K100 FPGA. The implemented prototype exhibits a latency of 110 ns and uses 32% of the logic cells of the device. When applied to MPEG-2 standard benchmark scenes, on average 3.5 symbols are decoded per cycle.

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A parallel decoder of programmable Huffman codes

Cited by 32 publications

References 8 publications

FPGA-based architecture for hardware compression/decompression of wide format images

FPGA-based architecture for hardware compression/decompression of wide format images

Multiple-symbol parallel decoding for variable length codes

Parallel multiple-symbol variable-length decoding

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