Parallel multiple-symbol variable-length decoding

Abstract

In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N -bit buffer whose accumulated codelength is at most N . The proposed method partially breaks the recursive dependency related to the MPEG-2 VLD. All possible codewords in the buffer are detected in parallel and the sum of the codelengths is provided to the external shifter aligning the variable-length coded input stream for a new decoding cycle. Two length detection mechanisms are proposed: the first approach determines the length in a parallel/serial fashion and the second using a new device denoted as MultiplexedAdd. In order to prove feasibility and determine the limiting factors of our proposal, the parallel/serial codeword detector with 32-bit input has been described in behavioral non-optimized VHDL and mapped onto Altera' s ACEX EP1K100 FPGA. The implemented prototype exhibits a latency of 110 ns and uses 32% of the logic cells of the device. When applied to MPEG-2 standard benchmark scenes, on average 3.5 symbols are decoded per cycle.

Dynamically reconfigurable VLD circuit

“…These The 13th IEEE International Symposium on Consumer Electronics (ISCE2009) VLD circuits are classified in three approaches: the serial architecture (tree-based architecture), bit-parallel processing architecture, and a variable input/output rate multiple-symbol decoding architecture [1][2][3].…”

Multiple-symbol parallel decoding for variable length codes

“…The work is based on the work reported earlier in [11]. The main contributions of this paper are the following.…”