2010 International Conference on Field-Programmable Technology 2010
DOI: 10.1109/fpt.2010.5681458
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A parallel FPGA design of the Smith-Waterman traceback

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Cited by 30 publications
(18 citation statements)
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“…Nawaz and colleagues use RVE with pre-computation (RVEP) to implement the two stages of the SW algorithm [3]. The authors are concerned with memory bandwidth bottleneck issues, caused by the transfer of data to a GPP; thus, they seek to reduce the required bandwidth by storing the direction vectors alone and performing the TB process on the FPGA.…”
Section: Previous Workmentioning
confidence: 99%
See 1 more Smart Citation
“…Nawaz and colleagues use RVE with pre-computation (RVEP) to implement the two stages of the SW algorithm [3]. The authors are concerned with memory bandwidth bottleneck issues, caused by the transfer of data to a GPP; thus, they seek to reduce the required bandwidth by storing the direction vectors alone and performing the TB process on the FPGA.…”
Section: Previous Workmentioning
confidence: 99%
“…Most of them do not present a full implementation of the algorithms and the traceback (TB) process is usually performed in a general purpose processor (GPP); however, various techniques are used to accelerate the original algorithm, such as linear recursive variable expansion (RVE) implementations [2], [3]; incremental approaches [4]; systolic arrays [5], and other simplifications of the algorithm. This paper presents a full implementation of the SW algorithm, by using a systolic array that performs the forward process, followed by a TB unit that generates the optimal sequence alignment, seeking to avoid bottleneck problems when trying to access external memory or performing calculations on a GPP.…”
Section: Introductionmentioning
confidence: 99%
“…Figura 6. Barrido de antidiagonal en antidiagonal Fuente: Elaboración propia Propuesta similar se observa en el trabajo de Nawaz et al (2010) para abordar el problema usando el procesamiento paralelo utilizando con un circuito integrado configurable, una FPGA ("Field Programmable Gate Array") (Nawaz et al, 2010), en el cual también refiere al llenado de antidiagonal en antidiagonal, y propone realizarlo por bloques en cada ciclo como se muestra en la figura 7. Como se puede apreciar, estas ideas han sido desarrolladas con hardware especializado pero en la actualidad contamos con librerías que pueden ayudar a resolver este problema, y hardware de propósito general con múltiples núcleos; no hay difusión de un algoritmo que realice tal recorrido de antidiagonal en antidiagonal para un proceso paralelo, la propuesta algorítmica se describe en la siguiente sección.…”
Section: Trabajos Previosunclassified
“…These solutions range from parallel implementations running in Graphics Processing Units (GPUs) [6] to dedicated hardware accelerators. Nevertheless, unidimensional (linear) systolic arrays are the most frequently adopted structures [8][9][10]. Nevertheless, unidimensional (linear) systolic arrays are the most frequently adopted structures [8][9][10].…”
Section: Introductionmentioning
confidence: 99%
“…The exception is observed in [15] and [10], where hardware architectures that also accelerate the traceback phase were recently presented. The exception is observed in [15] and [10], where hardware architectures that also accelerate the traceback phase were recently presented.…”
Section: Introductionmentioning
confidence: 99%