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A highly efficient video downscaling algorithm for any arbitrary integer scaling factor performed in a hybrid pixel transform domain is proposed. This algorithm receives the encoded DCT coefficient blocks of the input video sequence and efficiently computes the DCT coefficients of the scaled video stream. The involved steps are properly tailored so that all operations are performed using the encoding standard block structure, independently of the adopted scaling factor. As a result, the proposed algorithm offers a significant optimization of the computational cost without compromising the output video quality, by taking into account the scaling mechanism and by restricting the involved operations in order to avoid useless computations. In order to meet any system needs, an optional and possible combination of the presented algorithm with high-order AC frequency DCT coefficients discarding techniques is also proposed, providing a flexible and often required complexity scalability feature and giving rise to an adaptable tradeoff between the involved scalable computational cost and the resulting video quality and bit rate. Experimental results have shown that the proposed algorithm provides significant advantages over the usual DCT decimation approaches, both in terms of the involved computational cost, the output video quality, and the resulting bit rate. Such advantages are even more significant for scaling factors other than integer powers of 2 and may lead to quite high PSNR gains.

Efficient VLSI architectures for motion estimation using the full-search block-matching algorithm are proposed in this paper. These structures are based on an improved and more efficient two-dimensional single-array architecture with minimum latency, maximum throughput, and full utilization of the hardware resources. This optimized architecture is extended to a class of fully parameterizable multiple array architectures that combine both pipelining and parallel processing techniques and provide the ability to configure the processors according to the setup parameters, the processing time and the circuit area specified limits. The development of a single-array processor in a single-chip based on a 0.25-m CMOS technology process proves the practical interest of the proposed architecture for implementing real-time motion estimators.

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