BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment

Neves, Nuno; Sebastiao, Nuno; Patrício, André; Matos, David R.; Pfister, Tomas; Flores, Paulo; Roma, Nuno

doi:10.1109/asap.2013.6567581

Cited by 10 publications

(23 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Current problems of great concern in SW algorithm are computations and spaces complexity, which required powerful algorithm(s) to utilize the power of parallel machines. Implementing SW algorithm in parallel platforms plays a key role in sequences comparisons problems in order [16][17][18][19][22][23][24][25][26][27]. However, a serious weakness with this architecture is the limitation and constraint of fixed sizes of memory available for all shared processors.…”

Section: Discussionmentioning

confidence: 99%

“…Most current discussions in local sequence alignment focus on multicore architectures with shared memory such as divide and conquer techniques [16][17][18], striped SW [19][20][21][22], Instruction-set Processor (ASIP) architecture [23], data compression [24,25], genome assembly (re-sequence) algorithms [26,27], and Symmetric Multi-Processing (SMP) architecture [28,29]. This section discusses in detail these algorithms along with their advantage and disadvantage.…”

Section: Fig 3: Dual Core and Quad Core In Multicores Platformsmentioning

confidence: 99%

“…Neves, et al [23], extend an algorithm to work on Application Specific Instruction Processor (ASIP) architecture dedicated for sequences alignment problems. Fine grain is obtained by adopting pipeline architecture for SIMD instructions, while coarse grain is obtained by using multicore of multiple ASIPs with a shared memory architecture.…”

Section: Instruction-set Processor Architecture (Ipa)mentioning

confidence: 99%

See 2 more Smart Citations

Shared Memory and Hardware Utilizations for the Parallelization of Local Sequences Alignment using SW Algorithm: A Review

Eltayeeb¹,

Latiff²,

Isnin³

2015

IJCA

View full text Add to dashboard Cite

It is becoming increasingly difficult to ignore the importance of aligning DNA and Protein sequences to infer properties of new sequences from well-known reference sequences established and sorted in genetics databanks. Many studies in recent years have focused on different implementations of Sequences Alignment Problems (SAP). However, researcher confused with the ambiguous classification of the SAP. This paper is set out mainly to review, investigate, and analysis current trends in shared memory and hardware implementation of local SAP using Smith-Waterman algorithm. The literatures are addressing and evaluating in order to highlight their advantages and disadvantages.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Fig 3: Dual Core and Quad Core In Multicores Platformsmentioning

confidence: 99%

Section: Instruction-set Processor Architecture (Ipa)mentioning

confidence: 99%

See 1 more Smart Citation

Shared Memory and Hardware Utilizations for the Parallelization of Local Sequences Alignment using SW Algorithm: A Review

Eltayeeb¹,

Latiff²,

Isnin³

2015

IJCA

View full text Add to dashboard Cite

show abstract

“…[19] presents another application field of ASIPs, namely encryption standards, which also demand a high computation performance. [20] presents a highthroughput ASIP with specialized Single Instruction Multiple Data (SIMD) instructions frequently used in biological sequence alignment algorithms. All the above mentioned works describe typical ASIP architectures in a sense that they include application-specific pipelines, which operate according to a stored program.…”

Section: Application-specific Instruction Set Processorsmentioning

confidence: 99%

A proposed synthesis method for Application-Specific Instruction Set Processors

Horváth

Hosszú

Kovács

2015

Microelectronics Journal

View full text Add to dashboard Cite

a b s t r a c tDue to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.

show abstract

“…Other architectures are also explored for accelerating the alignment of DNA sequences. In [11], a single instruction multiple data (SIMD)-based architecture is implemented on an application-specific instruction-set processor (ASIP) for aligning DNA sequences.…”

mentioning

confidence: 99%