Efficient and configurable full-search block-matching processors

Roma, Nuno; Sousa, Leonel

doi:10.1109/tcsvt.2002.806818

Cited by 40 publications

(29 citation statements)

References 13 publications

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“…There are many other block matching algorithms (Nuno, 2002) and their variants available, but differs in the manner how they select the candidate for comparison and what is the motion vector resolution. Although, the full search algorithm is the best one in terms of the quality of the predicted image and its resolution of the motion vector it is very computationally intensive.…”

Section: Fast Search Algorithmsmentioning

confidence: 99%

H.264 Motion Estimation and Applications

Krishnan¹,

Gangadharan²,

Kumar³

2012

Video Compression

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Section: Fast Search Algorithmsmentioning

confidence: 99%

H.264 Motion Estimation and Applications

Krishnan¹,

Gangadharan²,

Kumar³

2012

Video Compression

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“…Reference [88] modified the 1-D linear array in [75] to support half-pixel precision, AP mode, PB mode, and RRU mode for H.263+. Reference [89] improved the architecture in [74] by changing the snake scan of search positions to regular column scan (top to bottom and then left to right) and using a circular shift scheme for PEs with half-reduced SRs. Reference [90] worked on an architecture design of variable block sizes ME for H.264/AVC.…”

Section: Fsbma Architecturesmentioning

confidence: 99%

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Huang

Chen

Tsai

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

138

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Abstract. Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hardware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same.

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“…For example, reference [11] is the extension of [5]. Reference [12] is proposed based on [9], and reference [13] combined [10] with multilevel successive elimination algorithm [14], [15]. Reference [16] is the extension of [6].…”

Section: Impact Of Supporting Vbsme In Different Hardware Architementioning

confidence: 99%

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Chen

Chien

Huang

et al. 2006

IEEE Trans. Circuits Syst. I

211

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Abstract-Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intralevel classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.Index Terms-Block matching, H.264/AVC, motion estimation (ME), variable block size, very large scale integration (VLSI) architecture.

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Efficient and configurable full-search block-matching processors

Cited by 40 publications

References 13 publications

H.264 Motion Estimation and Applications

H.264 Motion Estimation and Applications

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

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