A parallel genetic approach to the gate sizing problem of VLSI integrated circuits

Benkhider, S.; Boumghar, F.; Baba-Ali, Ahmed Riadh

doi:10.1109/icm.2000.916438

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…The methods for MO optimisation in Refs. [32,33] both are still based on scalarised cost functions. More recently, gate-sizing-based soft error optimisation using MOEAs is proposed in Ref.…”

Section: Discrete Gate Sizing For Ppa Optimisationmentioning

confidence: 99%

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

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Modern electronic design automation (EDA) tools can handle the complexity of state-ofthe-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed multi-objective electronic design automation flow (MOEDA) framework to ISCAS-85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved.

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Section: Discrete Gate Sizing For Ppa Optimisationmentioning

confidence: 99%

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

View full text Add to dashboard Cite

show abstract

“…In earlier works, typical heuristic techniques like genetic algorithms were applied to solving gate sizing problems. The methods for multi-objective optimisation in [31] and [32] both are still based on scalarized cost functions. More recently, gate-sizing-based soft error optimisation using MOEAs is proposed in [11] but its multi-objectives are soft error rate, critical path delay and area.…”

Section: Discrete Gate Sizing For Ppa Optimisationmentioning

confidence: 99%

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Cao¹,

Bale²,

Trefzer

2021

Preprint

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Modern electronic design automation (EDA) tools can handle the complexity of state-of-the-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independent-optimised design step, overhead and inefficiency can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space, but has the potential to provide solutions with improved performance. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, preceding physical implementation, through multi-objective population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is capable of expanding the design space, offering a set of Pareto-optimised trade-off solutions for different case-specific utilisation. We have applied the proposed MOEDA framework to ISCAS-85 benchmark circuits using a commercial 65nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow, and how simultaneously a significant improvement in PPA metrics is achieved.

show abstract

Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells

Cao

Bale

Trefzer

2021

IEEE Trans. Circuits Syst. I

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A parallel genetic approach to the gate sizing problem of VLSI integrated circuits

Cited by 3 publications

References 4 publications

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells

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