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This paper describes the implementation of a software CAD (Computer Aided Design) tool, applied to the sizing problem of standard cells VLSI integrated circuits. Unfortunately the sizing problem belongs to the class of NP-complete problems, and the size of VLSI circuits may be huge. As a consequence, we studied heuristic solutions in order to solve this problem. This software performs circuit timing optimization, based on an evolutionary approach. The genetic algorithm is a meta-heuristic which gives nearoptimal solutions with polynomial running times.

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