A parallel implementation of sequential minimal optimization on FPGA

Noronha, Daniel Holanda; Torquato, Matheus F.; Fernandes, Marcelo A. C.

doi:10.1016/j.micpro.2019.06.007

Cited by 27 publications

(19 citation statements)

References 8 publications

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“…The coefficient w and bias b of the regression function are processed by solving the Langrage multiplier in Equation 4, and the regression function f (x) after training is expressed by the Equation (5). The kernel function type used in the following sections is Radial Basis Function (RBF), and the expression is shown in Equation (6).…”

Section: Principle Of ε-Svrmentioning

confidence: 99%

“…For the solution of the optimization problem in Equation 4, the commonly used method include SMO [5], SGD [6], etc. The SMO only needs to update two parameters in each iteration, which has the characteristics of small calculation amount and high precision.…”

Section: Principle Of ε-Svrmentioning

confidence: 99%

“…The pipelined optimization is used to improve the bandwidth usage of existing memory block, but the bandwidth of on-chip memory becomes a bottleneck limiting the execution efficiency of training. From the analysis of the SMO in [5], the length of the matrix G is twice the number of samples. Usually the matrix is stored in a single BRAM, and only one element of matrix can be updated in a single cycle.…”

Section: Array Partition Optimizationmentioning

confidence: 99%

“…The implementation of SVR using FPGA has attracted a large number of researchers. Noronha et al proposes a parallel FPGA implementation of the Sequential Minimal Optimization (SMO) of SVM [5]. After the parallel implementation, SVM is validated by bit-accurate simulation.…”

Section: Introductionmentioning

confidence: 99%

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Research and Implementation of ε-SVR Training Method Based on FPGA

Liu

et al. 2019

Electronics

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Online training of Support Vector Regression (SVR) in the field of machine learning is a computationally complex algorithm. Due to the need for multiple iterative processing in training, SVR training is usually implemented on computer, and the existing training methods cannot be directly implemented on Field-Programmable Gate Array (FPGA), which restricts the application range. This paper reconstructs the training framework and implementation without precision loss to reduce the total latency required for matrix update, reducing time consumption by 90%. A general ε-SVR training system with low latency is implemented on Zynq platform. Taking the regression of samples in two-dimensional as an example, the maximum acceleration ratio is 27.014× compared with microcontroller platform and the energy consumption is 12.449% of microcontroller. From the experiments for the University of California, Riverside (UCR) time series data set. The regression results obtain excellent regression effects. The minimum coefficient of determination is 0.996, and running time is less than 30 ms, which can meet the requirements of different applications for real-time regression.

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Section: Principle Of ε-Svrmentioning

confidence: 99%

Section: Principle Of ε-Svrmentioning

confidence: 99%

Section: Array Partition Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Research and Implementation of ε-SVR Training Method Based on FPGA

Liu

et al. 2019

Electronics

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“…such as the tactile Internet [21,22], the Internet of Things (IoT) and Industry 4.0, where the problems associated with processing, power, latency and miniaturization are fundamental. Robotic manipulators used on tactile internet need a high-throughput and ultra-low-latency control system, and this can be achieved with dedicated hardware [21].The development of dedicated hardware, in addition to speeding up parallel processing, makes it possible to operate with clocks adapted to low-power consumption [23,24,25,26,27,28,29]. The works presented in [30,31,32,33,34,35,36,37] propose implementations of FS on reconfigurable hardware (Field Programmable Gate Array -FPGA), showing the possibilities associated with the acceleration of fuzzy inference processes having a high degree of parallelization.…”

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confidence: 99%

Proposal of Takagi–Sugeno Fuzzy-PI Controller Hardware

Silva

Lopes

Valderrama

et al. 2020

Sensors

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This work proposes dedicated hardware for an intelligent control system on Field Programmable Gate Array (FPGA). The intelligent system is represented as Takagi-Sugeno Fuzzy-PI controller. The implementation uses a fully parallel strategy associated with a hybrid bit format scheme (fixed-point and other floatingpoint). Two hardware designs are proposed; the first one uses a single clock cycle processing architecture, and the other uses a pipeline scheme. The bit accuracy was tested by simulation with a non linear control system of robotic manipulator. The area, throughput, and dynamic power consumption of the implemented hardware are used to validate and compare the results of this proposal. The results achieved allow that the proposal hardware can use in several applications with high-throughput, low-power and ultra-low-latency restrictions such as teleportation of robot manipulators, tactile internet, industrial automation in industry 4.0, and others. such as the tactile Internet [21,22], the Internet of Things (IoT) and Industry 4.0, where the problems associated with processing, power, latency and miniaturization are fundamental. Robotic manipulators used on tactile internet need a high-throughput and ultra-low-latency control system, and this can be achieved with dedicated hardware [21].The development of dedicated hardware, in addition to speeding up parallel processing, makes it possible to operate with clocks adapted to low-power consumption [23,24,25,26,27,28,29]. The works presented in [30,31,32,33,34,35,36,37] propose implementations of FS on reconfigurable hardware (Field Programmable Gate Array -FPGA), showing the possibilities associated with the acceleration of fuzzy inference processes having a high degree of parallelization. Other works propose specific implementations of Fuzzy Control Systems (FCS) using the Fuzzy Mamdani Inference Machine (M-FIM) and the Takagi-Sugeno Fuzzy Inference propose the Takagi-Sugeno hardware acceleration for other types of application fields. This work aims to develop a new hardware proposal for a Fuzzy-PI controller with TS-FIM. Unlike most of the works presented, this project offers a fully parallel scheme associated with a hybrid platform using fixed-point and floating-point representations. Two TS-FIM hardware modules have been proposed, the first (here called TS-FIM module one-shot) takes one sample time to execute the TS-FIM, and the second (here called as TS-FIM module pipeline) uses registers inside the TS-FIM. Two Fuzzy-PI controller hardware have been proposed, one for the TS-FIM one-shot module and another for the TS-FIM module pipeline. The proposed hardware have been implemented, tested and validated on a Xilinx Virtex 6 FPGA. The synthesis results, in terms of size, resources and throughput, are presented according to the number of bits and the type of numerical precision. Already, the physical area on the target FPGA reaches less than 7%. The implementation achieved a throughput between 10 and 18Msps (Mega samples per second), and between 490and 882 Mfl...

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