Proposal of Takagi–Sugeno Fuzzy-PI Controller Hardware

Abstract

This work proposes dedicated hardware for an intelligent control system on Field Programmable Gate Array (FPGA). The intelligent system is represented as Takagi-Sugeno Fuzzy-PI controller. The implementation uses a fully parallel strategy associated with a hybrid bit format scheme (fixed-point and other floatingpoint). Two hardware designs are proposed; the first one uses a single clock cycle processing architecture, and the other uses a pipeline scheme. The bit accuracy was tested by simulation with a non linear control system of robotic manipulator. The area, throughput, and dynamic power consumption of the implemented hardware are used to validate and compare the results of this proposal. The results achieved allow that the proposal hardware can use in several applications with high-throughput, low-power and ultra-low-latency restrictions such as teleportation of robot manipulators, tactile internet, industrial automation in industry 4.0, and others. such as the tactile Internet [21,22], the Internet of Things (IoT) and Industry 4.0, where the problems associated with processing, power, latency and miniaturization are fundamental. Robotic manipulators used on tactile internet need a high-throughput and ultra-low-latency control system, and this can be achieved with dedicated hardware [21].The development of dedicated hardware, in addition to speeding up parallel processing, makes it possible to operate with clocks adapted to low-power consumption [23,24,25,26,27,28,29]. The works presented in [30,31,32,33,34,35,36,37] propose implementations of FS on reconfigurable hardware (Field Programmable Gate Array -FPGA), showing the possibilities associated with the acceleration of fuzzy inference processes having a high degree of parallelization. Other works propose specific implementations of Fuzzy Control Systems (FCS) using the Fuzzy Mamdani Inference Machine (M-FIM) and the Takagi-Sugeno Fuzzy Inference propose the Takagi-Sugeno hardware acceleration for other types of application fields. This work aims to develop a new hardware proposal for a Fuzzy-PI controller with TS-FIM. Unlike most of the works presented, this project offers a fully parallel scheme associated with a hybrid platform using fixed-point and floating-point representations. Two TS-FIM hardware modules have been proposed, the first (here called TS-FIM module one-shot) takes one sample time to execute the TS-FIM, and the second (here called as TS-FIM module pipeline) uses registers inside the TS-FIM. Two Fuzzy-PI controller hardware have been proposed, one for the TS-FIM one-shot module and another for the TS-FIM module pipeline. The proposed hardware have been implemented, tested and validated on a Xilinx Virtex 6 FPGA. The synthesis results, in terms of size, resources and throughput, are presented according to the number of bits and the type of numerical precision. Already, the physical area on the target FPGA reaches less than 7%. The implementation achieved a throughput between 10 and 18Msps (Mega samples per second), and between 490and 882 Mfl...

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“…Another outcome of using the architecture was low consumption systems. As presented in [41] there is a strong dependency between operational clock frequency and the dynamic power. Using the clock rate lower than the maximum theoretical operating frequency causes a decrease in the dynamic power, making it possible to reduce energy consumption in applications where the processing speed is not limited and/or there is a need for low energy consumption.…”

Fully Parallel Implementation of Otsu Automatic Image Thresholding Algorithm on FPGA

“…The dynamic power consumption can be expressed as where is the dynamic power consumption, is the number of hardware components, is the frequency and is the supply voltage. The frequency at which a circuit can operate is proportional to the voltage [ 12 , 33 ]. Thus, the Equation ( 21 ) can be rewritten as …”

“…The first column indicates the number of n PNH . Meanwhile, from the second to fourth columns are shown, respectively, the image processing time, t I , defined according to Equation ( 13), the initial system latency, D, according to Equation (11) and the throughput, th, which in this work consists of the number of images processed per second (IPS), determined through Equation (12). According to Equation ( 13), the processing time of an image depends on its size.…”

“…According to (12), and ( 13), Equation ( 15) can be rewritten as Equation ( 16), allows one to define t I values as…”

“…This therefore allows applications to achieve real-time or near real-time processing. The FPGA allows the exploitation of the algorithm parallelization and the development of dedicated hardware to obtain performance improvement [9][10][11][12][13][14][15]. However, FPGA implementations found in the literature are often developed with sequential processing schemes in some stages of the Otsu algorithm, limiting the hardware's processing speed [16][17][18][19][20][21].…”