A parallelized layered QC-LDPC decoder for IEEE 802.11ad

Balatsoukas‐Stimming, Alexios; Preyss, Nicholas; Cevrero, Alessandro; Burg, Andreas; Roth, Christoph

doi:10.1109/newcas.2013.6573590

Cited by 14 publications

(5 citation statements)

References 10 publications

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“…Based on the channel observation, it is clear that the wireless VR system over 60 GHz RFIC should recover a number of burst errors. For some specifications targeting the high-speed near-field wireless communications, several candidates can support such a channel condition with different types of codes including low-density parity-check (LDPC) codes targeting the data rate of more than 6 Gbps [9][10][11][12]17]. However, the previous standards are normally defined to support various applications and thus they include several complicated processing steps to ensure the data integrity for different transmitting scenarios.…”

Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%

“…If we directly adopt the high-speed near-field communication standards [6][7][8], however, it is inefficient to give the immersive user-level experience due to the long transmission latency caused by the iterative error recovery algorithms associated with complex interleaving schemes [9][10][11][12]. Supporting the transmission rate of over 6 Gbps, for example, the recent WiGig standard uses a number of baseband operations including the scrambler, the FFT-based processing, the high-speed analog-to-digital conversion, and the iterative low-density parity-check (LDPC) error-correction code (ECC), requiring the transmission delay of more than 5 ms [13].…”

Section: Introductionmentioning

confidence: 99%

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High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

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Section: Baseband Processing With Block-level Interleaved-bch Codesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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“…An integrated early termination mechanism saves energy in the high SNR regimes. A more detailed description of the LDPC architecture is given in [12].…”

Section: Low-density Parity Check (Ldpc) Channel Decodermentioning

confidence: 99%

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Preyss¹,

Senning²,

Burg³

et al. 2015

2015 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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Abstract-We present a digital baseband ASIC for 60 GHz singlecarrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.

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“…Due to their excellent error correction performance such as high coding gain, low error-floor, low cost, and high throughput capabilities, they have found extensive applications in modern communication systems. For instance, LDPC codes have increasingly adapted in various applications such as in storage devices [7], wired and wireless communication standards [8][9][10], IEEE 802.11 [11], the Second-Generation Satellite Digital Video Broadcast (DVB-S2) [9], and Advanced Television System Committee (ATSC) [12]. In recent years, many studies have focused on one subclass of LDPC codes known as Quasi-Cyclic LDPC (QC-LDPC) codes [13].…”

Section: Introductionmentioning

confidence: 99%

Further Improvements in Decoding Performance for 5G LDPC Codes Based on Modified Check-Node Unit

Tran-Thi¹,

Nguyen-Ly²,

Hoang³

2023

RADIOENGINEERING

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One of the most important units of Low-Density Parity-Check (LDPC) decoders is the Check-Node Unit. Its main task is to find the first two minimum values among incoming variable-to-check messages and return check-tovariable messages. This block significantly affects the decoding performance, as well as the hardware implementation complexity. In this paper, we first propose a modification to the check-node update rule by introducing two optimal offset factors applied to the check-to-variable messages. Then, we present the Check-Node Unit hardware architecture which performs the proposed algorithm. The main objective of this work aims to improve further the decoding performance for 5 th Generation (5G) LDPC codes. The simulation results show that the proposed algorithm achieves essential improvements in terms of error correction performance. More precisely, the error-floor does not appear within Bit-Error-Rate (BER) of 10 -8 , while the decoding gain increases up to 0.21 dB compared to the baseline Normalized Min-Sum, as well as several state-ofthe-art LDPC-based Min-Sum decoders.

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A parallelized layered QC-LDPC decoder for IEEE 802.11ad

Cited by 14 publications

References 10 publications

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Further Improvements in Decoding Performance for 5G LDPC Codes Based on Modified Check-Node Unit

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