A Parameter Extraction Methodology for Graphene Field-Effect Transistors

Jeppson, Kjell

doi:10.1109/ted.2023.3239331

Cited by 6 publications

(3 citation statements)

References 22 publications

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“…For this reason, the model defined hereafter considers VGS ≫ VDirac, where dominant electron conduction occurs, but the methodology is equally valid for hole conduction at VGS ≪ VDirac. In fact, a combined analysis would also cover the transition region (i.e., V GS around V Dirac ) [14].…”

Section: Gate Bias-dependent Modelingmentioning

confidence: 99%

“…RCγ is the access resistance associated to the contact region and the ungated graphene region; thus, it is inferred that RCch = 0. The other resistance contribution independent of the gate voltage is Rθγ, which accounts for the mobility degradation within the graphene [14]. Finally, the bias-dependent term in ( 6) can be expressed as [11]:…”

Section: Gate Bias-dependent Modelingmentioning

confidence: 99%

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Characterization of the Intrinsic and Extrinsic Resistances of a Microwave Graphene FET Under Zero Transconductance Conditions

Ribero-Figueroa,

Pacheco-Sanchez,

Mansouri

et al. 2023

IEEE Trans. Electron Devices

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Graphene field-effect transistors exhibit negligible transconductance under two scenarios: for any gate-to-source voltage when the drain-to-source voltage is set to zero, and for an arbitrary drain-to-source voltage provided that the gate-to-source voltage equals the Dirac voltage. Hence, extracting the channel and the parasitic series resistances from S-parameters under these conditions enables analyzing their dependence on the gate and drain biases. This is fundamental to assess the portion of the output resistance that is controlled by the gate. Besides, the drain bias dependence of the drain and source resistances is also evidenced. Within the proposal, resistive components accounting for the lossy nature of the gate capacitance are incorporated into the model, which exhibits a broadband correlation with experimental data. This avoids the series resistances to be considered as frequency dependent in the model.

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Section: Gate Bias-dependent Modelingmentioning

confidence: 99%

Section: Gate Bias-dependent Modelingmentioning

confidence: 99%

Characterization of the Intrinsic and Extrinsic Resistances of a Microwave Graphene FET Under Zero Transconductance Conditions

Ribero-Figueroa,

Pacheco-Sanchez,

Mansouri

et al. 2023

IEEE Trans. Electron Devices

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“…Geometrical variations have been earlier experimentally studied for Dirac voltage VDirac (VTH equivalent in GFETs) in [17], [18], for Rd(s) in [20]- [23], for μ in [17], [23]- [27] and for impuritiesrelated residual charge nres in [26], however, such [23], [25], [28]. For the extraction of the basic parameters of the model (VDirac-related flat-band voltage VG0, Rd(s), μ, intrinsic mobility degradation θint [29] and nres-related parameter Δ) [5] several methodologies have been proposed [29], [30] where the one presented in [29], is applied here. IV hysteresis effects are also modelled, provided that trap-affected and trap-reduced measurement setups are available [31].…”

Section: Introductionmentioning

confidence: 99%

A Scalable Compact Model for the Static Drain Current of Graphene FETs

Mavredakis,

Pacheco-Sanchez,

Txoperena

et al. 2024

IEEE Trans. Electron Devices

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The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures IV experimental dependencies induced by geometrical scaling effects for graphene transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions, are thoroughly investigated, and semiempirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in research labs. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and hence, can contribute to the update of GFET technology from the research level to massive industry production.

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