A parameterized dataflow language extension for embedded streaming systems

2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies

Kellomäki

et al. 2008

Application specific instruction set processors (ASIP) allow designers to optimize the architecture of an embedded processor to meet the specific demands of a particular application. A complementary form of customization is provided by domain-specific models of computation (MoCs), which can expose the high level structure of applications that is useful for various kinds of optimizing design transformations. One such MoC is Synchronous Dataflow (SDF), which is used increasingly in the design and implementation of signal processing applications. In this paper, we develop an integration of SDF-and ASIP-oriented design flows, and use this integrated design flow to explore trade-offs in the space of hardware/software implementations. We also explore an approach to ASIP implementation in terms of "critical" and "non-critical" applications, which allows designers to tune the degree of specialization for a targeted ASIP. Our results show that single ASIP processor tuned for pair of critical applications saves 26% to 50% of area required for implementations of two applications on separate ASIPs and noncritical applications runs on such processor with in worst case 4.5% overhead for our selection of benchmarks.

Section: A From Domain-specific Models Of Computation To Implementationmentioning

confidence: 99%

An integrated ASIP design flow for digital signal processing applications

Guzma

2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies

Kellomäki

et al. 2008

“…2, where only a nite k-support de ned by the columns of the matrix P = diag (7,6) is displayed. Thus, n = V k, k ∈ {P ∩ 2 }, where P is the parallelepiped de ned by the columns of the matrix P. Notice that for an integral sampling matrix V , the number of integer points in V -denoted N(V ) -is equal to | det(V ) |.…”

Section: Arbitrary Samplingmentioning

confidence: 99%

“…In [2], Kee et al explore the application of PSDF techniques to eld programmable gate array implementation of the physical layer for 3GPP-Long Term Evolution (LTE). The integration of concepts related to parameterized data ow in language extensions for embedded streaming systems is explored in [7]. General techniques for analysis and veri cation of hierarchically recon gurable data ow graphs are explored in [14].…”

Section: Parameterized Data Owmentioning

confidence: 99%

Dynamic and Multidimensional Dataflow Graphs

Handbook of Signal Processing Systems

Deprettere

Keinert

2010

Much of the work to date on data ow models for signal processing system design has focused decidable data ow models that are best suited for onedimensional signal processing. In this chapter, we review more general data ow modeling techniques that are targeted to applications that include multidimensional signal processing and dynamic data ow behavior. As data ow techniques are applied to signal processing systems that are more complex, and demand increasing degrees of agility and exibility, these classes of more general data ow models are of correspondingly increasing interest. We begin with a discussion of two data ow modeling techniques -multi-dimensional synchronous data ow and windowed data ow -that are targeted towards multidimensional signal processing applications. We then provide a motivation for dynamic data ow models of computation, and review a number of speci c methods that have emerged in this class of models. Our coverage of dynamic data ow models in this chapter includes Boolean data ow, the stream-based function model, CAL, parameterized data ow, and enable-invoke data ow.

“…Other approach to introduce dataflow programming to DSP area is presented in SPEX language extension [6]. SPEX adds constructs to programming language (C++ in presented work) to allow programmers to describe inherent parallelism within a DSP system, including describing streaming computation and communication patterns of DSP systems.…”

Section: Related Workmentioning

confidence: 99%

Trade-offs in mapping high-level dataflow graphs onto ASIPs

Guzma

2008 International Symposium on System-on-Chip

Kellomäki

et al. 2008

Data-flow based design environments bring advantages of specification, validation and synthesis to embedded systems design by decoupling computation from transfer of data. The former is performed by actors, and data transfer between actors and an execution order of actors is determined by scheduling and buffering strategies. In this work, we examine code sizes and cycle counts resulting from combinations of scheduling and buffering techniques. The experiments were carried out by designing an application specific instructionset processor streamlined for each of the benchmarks, using a codesign environment called TeE. We also show what additional overhead is introduced when an architecture implemented using our approach is employed for an application outside its targeted domain.