A partially operated FFT/IFFT processor for low complexity OFDM modulation and demodulation of WiBro in-car entertainment system

Kim, Dong–Sun; Lee, Seung-Yerl; Chung, Dae-Won

doi:10.1109/tce.2008.4560111

Cited by 5 publications

(3 citation statements)

References 5 publications

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“…IFFT is the resort to achieve OFDM symbols . The data bits are correspond to frequency domain and IFFT convert signal in distinct domains to examine the mechanism.…”

Section: Inverse Fast Fourier Transformmentioning

confidence: 99%

An area‐efficient FFT processor for the OFDMA transceiver communication system

Nirmala

Sumathi²

2018

Concurrency and Computation

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Summary Orthogonal frequency division multiplexing (OFDM) is a well‐organized multiplexing scheme, which is long‐established in recent wireless and communication standards. OFDM resembles a system of exchanging information done with a nonflat channel called Discrete Multi‐Tone modulation (DMT) and Coded OFDM (COFDM). The data stream in this frequency modulation is divided across narrowband channels to limit interference and crosstalk. One of the extreme needs of OFDM is reasonable to be straight mean while sending and receiving systems. OFDM is extremely preferred for rapid data transmission and radio access method. In this paper, OFDM transceiver is carried out and implemented on FPGA. In addition, 128‐point IFFT/FFT pipelined architecture is proposed with the aim of optimizing area, frequency, and circuit complexity.

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“…IFFT is the resort to achieve OFDM symbols . The data bits are correspond to frequency domain and IFFT convert signal in distinct domains to examine the mechanism.…”

Section: Inverse Fast Fourier Transformmentioning

confidence: 99%

An area‐efficient FFT processor for the OFDMA transceiver communication system

Nirmala

Sumathi²

2018

Concurrency and Computation

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“…There have been several attempts to improve the efficiency of FFT units in OFDM applications by: (i) redesigning the arithmetic units [2][3][4][5][6]; (ii) modifying the memory controllers [7][8][9]; (iii) modifying the structure and adopting modulation aware multipliers [10]; and (iv) choosing the pipeline strategy and butterfly radix [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

“…Here, the hardware complexity was measured as number of equivalent adders. ‘Mixed‐radix [4], modified radix‐4 [6] and R2 3 ’ [9, 11, 13] based FFT designs were compared on the basis of performance, and the performance were affected by the choice of radix. For implementation purposes, R2‐SDF‐based architecture has been considered here, because of its simplicity and area efficiency.…”

Section: Introductionmentioning

confidence: 99%

Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

Arunachalam¹,

Raj²

2014

IET Circuits, Devices & Systems

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In an orthogonal frequency division multiplexing (OFDM)-based digital transmitter, the inverse fast Fourier transform (IFFT) processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the CooleyTukey-based decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed 'pass-logic'. These replacements can be possible because the inputs are bitwise with binary-phase shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for 8 to 128 points (N) were implemented with multipliers and 'pass-logics'. The performance improvements (PIs) of the proposed FFT/ IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the total power by 6.5%. The same implementation on an ASIC, consumed 28% less power and 27% lesser gates. In 128-point implementation, these PIs are more than those of the 64-point, thus PI is in upward trend as N increases. A chip for FFT processing as per IEEE 802.11a specifications (64-point, 16-bit data) is designed with pass-logics, which uses 24 947 gates and consumes 6.45 mW at 1.8 V, 20 MHz in 0.18 µm 1P6M CMOS process.

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Dual input radix 2³ SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme

Kim

Lee

2009

IEEE Trans. Consumer Electron.

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A partially operated FFT/IFFT processor for low complexity OFDM modulation and demodulation of WiBro in-car entertainment system

Cited by 5 publications

References 5 publications

An area‐efficient FFT processor for the OFDMA transceiver communication system

An area‐efficient FFT processor for the OFDMA transceiver communication system

Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

Dual input radix 2³ SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme

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A partially operated FFT/IFFT processor for low complexity OFDM modulation and demodulation of WiBro in-car entertainment system

Cited by 5 publications

References 5 publications

An area‐efficient FFT processor for the OFDMA transceiver communication system

An area‐efficient FFT processor for the OFDMA transceiver communication system

Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

Dual input radix 23 SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme

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Dual input radix 2³ SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme