Dual input radix 2<sup>3</sup> SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme

Kim, Dong–Sun; Lee, Seung-Yerl

doi:10.1109/tce.2009.5373805

Cited by 7 publications

(4 citation statements)

References 12 publications

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“…Higher radices have also been considered for the SDF FFT architecture. The literature includes SDF FFT architectures for radix-2 3 [2,52], radix-2 4 [24,25,51,54,66,72], and split radix [86]. Indeed, several radices of the form 2 k are considered in some works [21,29,77].…”

Section: The Sdf Fft Architecturementioning

confidence: 99%

A Survey on Pipelined FFT Hardware Architectures

Garrido

2021

J Sign Process Syst

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The field of pipelined FFT hardware architectures has been studied during the last 50 years. This paper is a survey that includes the main advances in the field related to architectures for complex input data and power-of-two FFT sizes. Furthermore, the paper is intended to be educational, so that the reader can learn how the architectures work. Finally, the paper divides the architectures into serial and parallel. This classification puts together those architectures that are conceived for a similar purpose and, therefore, are comparable.

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Section: The Sdf Fft Architecturementioning

confidence: 99%

A Survey on Pipelined FFT Hardware Architectures

Garrido

2021

J Sign Process Syst

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“…Main supporting idea of this method is that N 1 and N 2 , those are two-factor of N, are prime to each other. Input and output index mapping is done according to equation (6) and (7), respectively.…”

Section: B the Good-thomas Fft Algorithmmentioning

confidence: 99%

“…Implementing of different schemes of FFT algorithms and applications received much attention in literature [6][7][8][9][10]. The aim of this paper is to model and hardware description of different schemes of FFT approaches including CooleyTukey, Good-Thomas, Radix-2 and Rader methods by Verilog HDL and realization of them on Xilinx FPGA chip.…”

Section: Introductionmentioning

confidence: 99%

“…They consist of thousands of logic gates and some configurable logic blocks which make them an appropriate solution for prototyping the application specific integrated circuits (ASIC) with dedicated architectures for specified digital signal processing applications. The introduction of Verilog Hardware Description Language (HDL) [5] provided a modeling and simulation environment for fast prototyping digital circuits and systems on FPGA.Implementing of different schemes of FFT algorithms and applications received much attention in literature [6][7][8][9][10]. The aim of this paper is to model and hardware description of different schemes of FFT approaches including CooleyTukey, Good-Thomas, Radix-2 and Rader methods by Verilog HDL and realization of them on Xilinx FPGA chip.…”

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confidence: 99%

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Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

Singhal¹,

Goen²,

Mohapatrara³

2018

IJERMT

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Abstract:he Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware's like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs by developing our own FFT processor architecture. Keywords I. INTRODUCTIONIn the recent decades DFT has been playing several important roles in advanced applications such as image compression and reconstruction in biomedical images, audiology research for analyzing biomedical brain-stem speech signals, sound filtering, data compression, partial differential equations, and multiplication of large integers.The fast algorithms for DFT always look for DFT process to be fast, accurate and simple. Fast is the most important [5]. Since the introduction of the Fast Fourier Transform (FFT), Fourier analysis has become one of the most frequently used tool in signal/image processing and communication systems; The main problem when calculating the transform relates to construction of the decomposition, namely, the transition to the short DFT's with minimal computational complexity. The computation of unitary transforms is complicated and time consuming process. Since the decomposition of the DFT is not unique, it is natural to ask how to manage splitting and how to obtain the fastest algorithm of the DFT. The difference between the lower bound of arithmetical operations and the complexity of fast transform algorithms shows that it is possible to obtain FFT algorithms of various speed [2]. One approach is to design efficient manageable split algorithms. Indeed, many algorithms make different assumptions about the transform length [5]. The signal/image processing related to engineering research becomes increasingly dependent on the development and implementation of the algorithms of orthogonal or non-orthogonal transforms and convolution operations in modern computer systems. The increasing importance of processing large vectors and parallel computing in many scientific and engineering applications require new ideas for designing super-efficient algorithms of the transforms and their implementations [2].The hardware implementation of FFT approaches is a challenging issue where the digital signal processors (DSPs) and the field programmable gate array (FPGA) chips are two considering designing environments for implementing different schemes of FFT approaches.Recently, the FPGA techn...

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Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems

Shih

Chou

2018

ICT Express

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Dual input radix 2³ SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme

Cited by 7 publications

References 12 publications

A Survey on Pipelined FFT Hardware Architectures

A Survey on Pipelined FFT Hardware Architectures

Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems

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Dual input radix 23 SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme

Cited by 7 publications

References 12 publications

A Survey on Pipelined FFT Hardware Architectures

A Survey on Pipelined FFT Hardware Architectures

Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems

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Product

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Dual input radix 2³ SDF IFFT/FFT processor for wireless multi-channel real sound speakers using time division duplex scheme