An accurate and computationally efficient means of feature extraction of electromyographic (EMG) signal patterns has been the subject of considerable research effort in recent years. Quantitative analysis of EMG signals provides an important source of information for the classification of neuromuscular disorders. The objective of this study is to discriminate between normal (NOR), myopathic (MYO) and neuropathic (NEURO) subjects. The experiment consisted of 22 pathogenic (11 MYO and 11 NEURO) and 12 healthy persons. The signals were recorded at 30% Maximum Voluntary Contraction (MVC) for 5 seconds. Features of MUAPs extracted in time have been quantitatively analysed. We have used binary SVM for classification. Separation of normal subjects from neuromuscular disease subjects has an accuracy of 83.45%, whereas separation of subjects from the two types of subjects (myopathic and neuropathic) has an accuracy of 68.29% which is again high. 

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This paper present a comparative study between two works proposed for microstrip patch antenna dual band operations. The comparison is made between a dual-band planar antenna with a compact radiator for 2.4/5.2/5.8-GHz Wireless Local Area Network (WLAN) applications and a printed circular microstrip patch antenna with a four rectangular shape strip and co planar rectangular ground plane antenna. The comparative analysis between these two antennas consist of following parameters such as dimensions, bandwidth, gain, return loss, directivity etc.

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Abstract:he Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware's like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs by developing our own FFT processor architecture. Keywords I. INTRODUCTIONIn the recent decades DFT has been playing several important roles in advanced applications such as image compression and reconstruction in biomedical images, audiology research for analyzing biomedical brain-stem speech signals, sound filtering, data compression, partial differential equations, and multiplication of large integers.The fast algorithms for DFT always look for DFT process to be fast, accurate and simple. Fast is the most important [5]. Since the introduction of the Fast Fourier Transform (FFT), Fourier analysis has become one of the most frequently used tool in signal/image processing and communication systems; The main problem when calculating the transform relates to construction of the decomposition, namely, the transition to the short DFT's with minimal computational complexity. The computation of unitary transforms is complicated and time consuming process. Since the decomposition of the DFT is not unique, it is natural to ask how to manage splitting and how to obtain the fastest algorithm of the DFT. The difference between the lower bound of arithmetical operations and the complexity of fast transform algorithms shows that it is possible to obtain FFT algorithms of various speed [2]. One approach is to design efficient manageable split algorithms. Indeed, many algorithms make different assumptions about the transform length [5]. The signal/image processing related to engineering research becomes increasingly dependent on the development and implementation of the algorithms of orthogonal or non-orthogonal transforms and convolution operations in modern computer systems. The increasing importance of processing large vectors and parallel computing in many scientific and engineering applications require new ideas for designing super-efficient algorithms of the transforms and their implementations [2].The hardware implementation of FFT approaches is a challenging issue where the digital signal processors (DSPs) and the field programmable gate array (FPGA) chips are two considering designing environments for implementing different schemes of FFT approaches.Recently, the FPGA techn...