FPGA implementation and power efficient CORDIC based ADPLL for signal processing and application

Singhal, Akarshika; Goen, Anjana; Mohapatra, Tanutrushna

doi:10.1109/csnt.2017.8418560

Cited by 4 publications

(6 citation statements)

References 8 publications

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“…There are four main transformations used in PLLs: the Clarke Transform (abcαβ) [2], the Park Transform (αβ-dq) [2], the Hilbert Transform [1] and the SOGI Filter [3], used to generate orthogonal signals. These transformations will be discussed further on.…”

Section: Resultsmentioning

confidence: 99%

“…The phase shift between the reference and generated signal is estimated using the Coordinate Rotation Digital Computer algorithm (CORDIC). This algorithm has been a trusted technique, which has been used to compute elementary trigonometric functions by means of planar rotation or vectoring process [1]. In this case, the function implemented is the arctangent2, which receives an input signal (sine) and its quadrature (cosine).…”

Section: 6hilbert Based Pllmentioning

confidence: 99%

“…The Phase-Locked Loop (PLL) is a control loop system, where the output phase is compared with the phase of an input signal [1]. The purpose of this closed loop is to reduce the phase error between a reference signal and a generated signal, changing its frequency.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Review of Mathematical Transforms for Phase-Locked Loops Control

Plech¹,

Silva²,

Silva³

2022

Blucher Engineering Proceedings

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The mathematical transforms used in Phase-Locked Loops (PLLs) play a crucial role in their performance and functioning. Depending on the format of the control loop's input signal, noise level requirements and other requirements such as available computational power, one must choose which topology best suits a given application. This article will address the most used transforms and filters in the most common PLL topologies, such as the Clarke Transform, the Park Transform, the Second-Order Generalized Integrator (SOGI) filter and the Hilbert Transform. Finally, a comparison of the advantages and disadvantages of each of these methods is discussed.

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Section: Resultsmentioning

confidence: 99%

Section: 6hilbert Based Pllmentioning

confidence: 99%

See 1 more Smart Citation

A Review of Mathematical Transforms for Phase-Locked Loops Control

Plech¹,

Silva²,

Silva³

2022

Blucher Engineering Proceedings

View full text Add to dashboard Cite

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“…The developed error signal is equivalent to the variation in frequency of the output and input signal. It is given in (1). The PD output contains both the frequency and phase components.…”

Section: ) Digital Phase Detectormentioning

confidence: 99%

“…In the past years, the Phase Locked Loop (PLL) has become the widest technique for stability and frequency generation. ADPLL is one of the PLL's designs, but its component's nature is fully digital [1]. It is used for advanced communication systems like demodulators, modulators, synthesizers and frequency generators, carrier clocks and recovery [2].…”

Section: Introductionmentioning

confidence: 99%

A Novel Architecture of ADPLL Using Cordic Algorithm for Low-Frequency Application

Velamarthi Spandana,

2023

IJRITCC

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All Digital Phase Locked Loop (ADPLL) has many applications in digital communication. It is difficult for low-frequency applications to achieve the lock state quickly. Therefore, proposed a novel particle swarm based ADPLL (PS-ADPLL) with Coordinate Rotation Digital Computer (CORDIC) algorithm to attain the lock state of the ADPLL for the low-frequency applications. In the proposed architecture, the D flip-flop matches the frequency and the phase of the output and reference pulses and produces an error signals up and down signal. The up/down counter removes the higher frequency part and produces a carry and the borrow signal. These carry and borrow signals are then fed into the increment decrement counters to produce the output signal matching the frequency of the reference signal. However, the time delay is increased for low-frequency applications, which is critical for the lock state. So, the delay line length is calculated by the CORDIC algorithm and is optimized by the particle swarm activated in the phase detector to match the output pulse with the reference pulse and make ADPLL into a locked state. The presented PS-ADPLL is tested in FPGA. Furthermore, the performance parameters are evaluated and compared with other current techniques to calculate the improvement score.

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