A Pattern-Search Method for H.264/AVC CAVLC Decoding

Tseng, Shau-Yin; Hsieh, Tien-Wei

doi:10.1109/icme.2006.262720

Cited by 16 publications

(4 citation statements)

References 11 publications

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“…7) to speed up the CAVLC decoding algorithm. Detail information can be found in [22]. If the two-phase pattern search algorithm failed, original CAVLC decoding is applied.…”

Section: Cavlc Of the Entropy Decodingmentioning

confidence: 99%

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Chen

Liu

Yang

et al. 2010

J Sign Process Syst

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Two representative multimedia applications-AAC and H.264/AVC decoders on the parallel architecture core (PAC) SoC are introduced in the second part of the two introductory papers. The applications have been programmed on the PACDSP core and the PAC SoC to demonstrate the high-performance, low-power DSP computations and the effectiveness of the dynamic voltage and frequency scaling (DVFS) capability on the heterogeneous multicore SoC. First, techniques to exploit data-and instruction-level parallelisms existing in the application kernels are described for performance optimizations on the clustered VLIW architecture of PACDSP with the distributed register organization. Next, two variation techniques of asymmetric programming model are introduced by examples of decoders. Then, the energy efficiency of the programmable multimedia SoC is demonstrated using an innovative power-aware H.264/AVC decoder. Finally, a DVFS-aware framework for soft real-time video playback is provided by extending the power-aware decoding scheme. The work provides practical references of realizing multimedia applications on PAC SoC suitable for richfunction and resource constraint portable devices.

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“…7) to speed up the CAVLC decoding algorithm. Detail information can be found in [22]. If the two-phase pattern search algorithm failed, original CAVLC decoding is applied.…”

Section: Cavlc Of the Entropy Decodingmentioning

confidence: 99%

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Chen

Liu

Yang

et al. 2010

J Sign Process Syst

Self Cite

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“…Accordingly a two-phase pattern search algorithm is derived (as shown in Figure 4-1) to speedup the CAVLC decoding algorithm contained in the ED procedure executed on the MPU core. Detail information can be found in (Tseng, 2006).…”

Section: Entropy Decoding On Mpumentioning

confidence: 99%

Realization and Optimization of H.264 Decoder for Dual-Core Soc

Chen¹,

Chen²,

Luo³

et al. 2007

Proceedings of the Second International Conference on Signal Processing and Multimedia Applications

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This paper presents an H.264/AVC decoder realization on a dual-core SoC (System-on-Chip) platform by the well-designed macroblock level software partitioning. Furthermore, optimizations of the procedures executed on each core, and data movement between two cores are captured from software and hardware techniques. The evaluation results show that a video with D1 (720×480 pixels) resolution can reach realtime decoding by the implementation, which provides a valuable experience for similar designs.

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“…Driven by the progress of science and technology, multimedia applications on mobile devices are getting more and more popular [3][4][5][6]. However, the embedded processors used in the mobile devices don't have enough computation power to realize the complex H.264 video decoder in real-time.…”

Section: Introductionmentioning

confidence: 99%

“…In the algorithm-level optimization, we propose various techniques like fast interpolation scheme, zero-skipping technique for texture decoding, fast boundary strength decision for in-loop filtering, and pattern matching algorithm [3] for CAVLD. In the code-level optimization, we propose the design techniques of minimizing memory access and branch times.…”

Section: Introductionmentioning

confidence: 99%

Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications

Huang

Jian

Chu

et al. 2008

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

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In this paper, we propose a joint algorithm/code-level optimization scheme to make it feasible to perform real-time H.264/AVC video decoding software on ARM-based platform for mobile multimedia applications. In the algorithm-level optimization, we propose various techniques like fast interpolation scheme, zero-skipping technique for texture decoding, fast boundary strength decision for in-loop filtering, and pattern matching algorithm for CAVLD. In the code-level optimization, we propose the design techniques on minimizing memory access and branch times. The experimental result shows that we have reduced the complexity of H.264 video decoder up to 93% as compared to the reference software JM9.7. The optimized H.264 video decoder can achieve the QCIF@30Hz video decoding on an ARM9 processor when operating at 120MHz clock.

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A Pattern-Search Method for H.264/AVC CAVLC Decoding

Cited by 16 publications

References 11 publications

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part II: Application Programming

Realization and Optimization of H.264 Decoder for Dual-Core Soc

Joint algorithm/code-level optimization of H.264 video decoder for mobile multimedia applications

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