In this paper, a new implementation method is proposed for Context-Adaptive Variable Length Coding (CAVLC) used in H.264 Baseline Profile. We analyze the correlation between bit patterns and 4x4 (or 2x2) blocks and have an idea of a pattern-search method before CAVLC decoding. If a pattern is matched in our look-up table, we can skip the standard CAVLD procedure and reconstruct a block directly. However, if there is not any pattern matched in the table, we have to reconstruct a block by CAVLD. Our lookup tables are built up according to our statistics and analysis. The experimental results show that the performance can be improved 10% compared with the standard CAVLD procedure.

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We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standard. EBCOT Tier-1 accounts for more than 70% of encoding time due to extensive bit-level processing. Our architecture consists of a 16-bit parallel context formation module and a 3-stage pipelined arithmetic encoder. Compared with the known best design, we reduce 17% of the cycle count and have achieved within 5% of the theoretical lower bound. We have integrated our synthesizable RTL with an AMBA-AHB interface for SOC design. FPGA prototyping has been successfully demonstrated and substantial speedup achieved.