A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os

Inagi, Masato; Takashima, Yoshinori; Nakamura, Yūichi; Kajitani, Yoji

doi:10.1109/fpt.2006.270348

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…However, these work at the physical synthesis level where the netlist is at the gate level, compared to the high-level abstracted dataflow graph in HLS. In Inagi et al [2006], the authors have proposed an algorithm for circuit bipartitioning focusing on an implementation of time-multiplexed I/Os. Some facets of an improved version of the Fiducia-Matheyses algorithm are exploited in a multiway FPGA partitioning procedure called FART in Roncheng et al [1998].…”

Section: Related Workmentioning

confidence: 99%

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Sinha

Srikanthan

2014

ACM Trans. Des. Autom. Electron. Syst.

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Area efficiency in datapath synthesis is a widely accepted goal of high-level synthesis. Applications represented by their dataflow graphs are synthesized using resource sharing principles to reduce the area. However, existing resource sharing algorithms focus on absolute area reduction and maximal resource sharing. This kind of a design approach leads to constraints on how often, in terms of number of clock cycles, a new set of input data can be fed to an application. It also leads to very large multiplexers in case of very big dataflow graphs with hundreds of nodes. An adaptive dataflow graph partitioning algorithm is proposed that partitions a graph taking into account a user-defined constraint on how often a new set of input data (generally referred to as data initiation interval) is available. At the same time, a resource sharing algorithm is applied to such partitions in order to reduce area. Multiple design points are generated for a given dataflow graph with different area and time measures to enable a designer to make decisions. We demonstrate our graph partitioning algorithm using synthetically generated large dataflow graphs and on some benchmark applications. ACM Reference Format:Sharad Sinha and Thambipillai Srikanthan. 2014. Dataflow graph partitioning for area-efficient high-level synthesis with systems perspective.

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Section: Related Workmentioning

confidence: 99%

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Sinha

Srikanthan

2014

ACM Trans. Des. Autom. Electron. Syst.

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“…Circuit netlists can be represented as hypergraphs, where logic elements (or sometimes groups of elements) are graph nodes and the nets that connect the nodes are hyperedges. Netlist/Hypergraph partitioning based on variants of the KLFM algorithm [4] often optimize for metrics such as channel width/congestion, ease of routability, and operating frequency [5]. Some work has also examined multi-resource constraints for heterogeneous devices for KLFM [2] and other algorithms [3], but unlike our work, they do not integrate personality selection for multi-personality nodes into partitioning.…”

Section: Related Workmentioning

confidence: 99%

Multi-personality partitioning for heterogeneous systems

Gregerson

Chadha

Morrow

2013

2013 International Conference on Field-Programmable Technology (FPT)

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Abstract-Design flows use graph partitioning both as a precursor to place and route for single devices, and to divide netlists or task graphs among multiple devices. Partitioners have accommodated FPGA heterogeneity via multi-resource constraints, but have not yet exploited the corresponding ability to implement some computations in multiple ways (e.g., LUTs vs. DSP blocks), which could enable a superior solution. This paper introduces multi-personality graph partitioning, which incorporates aspects of resource mapping into partitioning. We present a modified multi-level KLFM partitioning algorithm that also performs heterogeneous resource mapping for nodes with multiple potential implementations (multiple personalities). We evaluate several variants of our multi-personality FPGA circuit partitioner using 21 circuits and benchmark graphs, and show that dynamic resource mapping improves cut size on average by 27% over static mapping for these circuits. We further show that it improves deviation from target resource utilizations by 50% over post-partitioning resource mapping.

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“…In [182], the authors have proposed an algorithm for circuit bi-partitioning focusing on an implementation of time-multiplexed I/Os. Some facets of an improved version of Fiducia-Matheyses algorithm are exploited in a multi-way FPGA partitioning procedure called FART in [183]. An integrated partitioning and synthesis approach for multi-FPGA reconfigurable computers is proposed in [184].…”

Section: G Graph Partitioning For Run Time Reconfigurationmentioning

confidence: 99%

Intelligent high level synthesis for customization on reconfigurable platforms

Sinha¹

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High level synthesis (HLS) using C/C++ has increasingly become a critical step in the realization of complex digital systems. One of the major research focus areas in this space has been to realize efficient synthesis of complex systems without violating stringent time-to-market constraints. Most of the related work cited in the literature has been mainly xi 6.2 Matrix size determination for matrix-matrix multiplication.

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A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os

Cited by 4 publications

References 6 publications

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Multi-personality partitioning for heterogeneous systems

Intelligent high level synthesis for customization on reconfigurable platforms

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