A performance evaluation of the multiple bus network for multiprocessor systems

Valero, Mateo; Llaberia, J.M.; Labarta, Jesús; Sanvicente, E.; Lang, T.

doi:10.1145/800040.801408

Cited by 12 publications

(9 citation statements)

References 9 publications

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“…In a buered system, the unsuccessful requests are queued in buers at the memory modules, and are resubmitted to the memory modules in the next cycle. Performance evaluation of both unbuered [3±9] and buered [10,11] crossbar and multiplebus systems have been reported in the literature. Good surveys of crossbar and multiple-bus systems appear in Refs.…”

Section: Computers and Electrical Engineering 27 (2001) 293±308mentioning

confidence: 99%

Effect of non-uniform memory request on the performance of buffered multiprocessor systems

Sayeed

Atiquzzaman

2001

Computers & Electrical Engineering

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Performance analysis of multiple-bus systems is usually carried out under the assumption of a uniform memory request model. Hot spots arising in multiprocessor systems give rise to non-uniform memory requests. It is known that a hot spot memory request pattern results in a signi®cant degradation in the performance of a buered multistage interconnection network. The aim of this research is to study the eect of hot spots on the performance of buered multiple-bus systems, and to compare the performance of buered and unbuered systems. Analytical models based on Markov chains have been developed to determine the bandwidth of buered multiple-bus systems in the presence of a hot spot memory request pattern. The models assume that unsuccessful memory requests are queued in the buers at the memory modules. Furthermore, processors with outstanding requests are not allowed to generate new requests. The model allows a fast and inexpensive method to evaluate the performance of a buered multiple-bus system in the presence of a hot spot memory request pattern. Ó

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Section: Computers and Electrical Engineering 27 (2001) 293±308mentioning

confidence: 99%

Effect of non-uniform memory request on the performance of buffered multiprocessor systems

Sayeed

Atiquzzaman

2001

Computers & Electrical Engineering

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“…This policy for handling rejected requests is implemented in the simulation model of [3]. Analytic models that capture this temporal dependence feature appear to be intractable except in those cases where B, M, and N are very small [8].…”

Section: Basic Modelmentioning

confidence: 99%

“…We will refer to this as the spatial independence assumption. A Markov chain model that avoids both of these assumptions is postulated by Valero et al in [8]; however, it is intractable for systems with more than about four processors. The same authors derive a somewhat simpler model assuming only temporal independence, which they term the memoryless property.…”

Section: Introductionmentioning

confidence: 99%

Analysis of multiple-bus interconnection networks

Mudge

Hayes

Buzzard

et al. 1986

Journal of Parallel and Distributed Computing

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The performance of multiple-bus interconnection networks for multiprocessor systems is analyzed, taking into account conflict arising from memory and bus interference. A discrete stochastic model of bandwidth is presented for systems in which each memory is connected either to all the buses or to a subset of the available buses. The effects of the assumptions made concerning independence among requests for different memories (spatial independence) and resubmission of blocked requests (temporal independence) are investigated systematically. The basic bandwidth model is extended to account for spatial dependence, and compared to previously proposed models. Finally, the various analytic models are shown to be in close agreement with simulation results. Q 1986 Academic Press, Inc.

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“…Because the crossbar cost becomes prohibitive in many real situations, other intereonnection networks have been proposed and analyzed to optimize the design at a given cost; that is the case of several degradating networks, such as : single-bus (2,3), multlple-bus (4,5,6) and shuffle-exchange (7).…”

Section: Introdgctionmentioning

confidence: 99%

Analysis and simulation of multiplexed single-bus networks with and without buffering

Griñó

Cortés

Lillo

et al. 1985

SIGARCH Comput. Archit. News

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Performance issues of a slngle-bus interconnection network for multlprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. Comparisons with equivalent crossbar systems are provided. It is shown how crossbar EBW values can be reached and exceeded when appropriate operation parameters are chosen in a multiplexed slngle-bus system. Another architectural feature is considered, concerning the utilization of buffers at the memory modules. With the buffering scheme, memory interference can be reduced so that the system performance is practically improved. I. INTRODgCTIONIn many multiprocessor systems, the shared memory is divided into independent modules, so that some type of interconnection network must exist to provide a communication path between processors and memory modules.Both the sharing of memory modules, and the interconnectlon network itself, contribute to the global system loss of efficiency. This performance reduction is due to : i) memory interference, 2) network degradation (if less than needed number of links is provided) and 3) network arbitration and llnk switching additional delay times.One of the first and most widely used interconnectlon network is the crossbar, (I) This network does not introduce degmadatlon, but due to memory conflicts its bandwidth is only 0.6 n when the number of processors (n) and the number of memory modules (m) are both large and equal,(1).Because the crossbar cost becomes prohibitive in many real situations, other intereonnection networks have been proposed and analyzed to optimize the design at a given cost; that is the case of several degradating networks, such as : single-bus (2,3), multlple-bus (4,5,6) and shuffle-exchange (7).Multiplexed networks operate in a way that allows the links to be occupied only during the time interval required to the processor requests to reach memory modules, or the memory modules to turn results back to processors. This multiplexed operation makes additional hardware necessary, but allows either greater network bandwidth, or lower number of links, or reduction in memory interference when more memory modules are provided for a given network cost. Summary and conclusions are provided in the last section of the paper. 2.-SYSTEM OPERATIONTo evaluate the system performance, the following operation assumptions are introduced:a) The system under study is composed of n processors and m memory modules.0149-7111/85/0000/0414501.00 © 1985 IEEE 414 b) The system basic cycle, as well as the bus transfer delay time, is a constant value, t. Arbitration delay is considered to be included in this value. c) Cycle time of all memory modules is the same and equal to r.t, where r is an integer value. d) Processor cycle is (r + 2) ~ t; all the processors are synchronized at the bus cycle. e) The processors requests are independent and equally distributed among the different memory modules, (21). f) After receiving the previous memory service, a process...

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A performance evaluation of the multiple bus network for multiprocessor systems

Abstract: In this paper we present a mathematical model to compute the bandwidth of the multiple bus interconnection network.

Cited by 12 publications

References 9 publications

Effect of non-uniform memory request on the performance of buffered multiprocessor systems

Effect of non-uniform memory request on the performance of buffered multiprocessor systems

Analysis of multiple-bus interconnection networks

Analysis and simulation of multiplexed single-bus networks with and without buffering

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