A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14&amp;#x00B5;A sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, Koji; Sugii, Nobuyuki; Usami, Kimiyoshi; Amano, Hideharu; Kobayashi, Kazutoshi; Pham, Cong‐Kha; Makiyama, Hideki; Yamamoto, Y.; Shinohara, Hirofumi; Iwamatsu, T.; Yamaguchi, Yasuo; Oda, H.; Hasegawa, Tetsuya; Okanishi, Shinobu; Yanagita, Hiroshi; Kamohara, S.; Kadoshima, Masaru; Maekawa, Kazuyuki; Yamashita, T.; Le, Duc; Yomogita, Takumu; Kudo, Masatoshi; Kitamori, Kuniaki; Kondo, Shuya; Manzawa, Yuuki

doi:10.1109/coolchips.2014.6842954

Cited by 18 publications

(8 citation statements)

References 2 publications

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“…We have confirmed a successful operation [24] of the proto-type ULV micro-controller chip as shown in Figure 11. This chip is composed of 32-bit RISC CPU with five-stage pipeline, 144 kByte SRAM, and interfaces (ROM, UART, SPI, and GP) and can be connected with sensors and rf modules 4 5 6 7 8 9 : ;…”

Section: Demonstration Of Ulv and Ulp Operation Of Logic Circuitssupporting

confidence: 65%

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Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Sugii

Yamamoto

Makiyama

et al. 2014

JLPEA

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Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive V th control

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Section: Demonstration Of Ulv and Ulp Operation Of Logic Circuitssupporting

confidence: 65%

“…Energy per cycle E as a function of operating voltage V dd for the "Perpetuum-Mobile" micro-controller chip[24].…”

mentioning

confidence: 99%

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Sugii

Yamamoto

Makiyama

et al. 2014

JLPEA

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“…Several publications have already demonstrated the merits of the FDSOI technology to improve energy efficiency of CMOS circuits at 65 nm [66] and 28 nm [67,68]. However, the general belief is that advantage of FDSOI and its body biasing capability is only limited to low-power, low-performance applications.…”

Section: Energy Efficient Computing In Fdsoi: a Case Study From Chinamentioning

confidence: 99%

Fully depleted SOI (FDSOI) technology

Cheng¹,

Khakifirooz

2016

Sci. China Inf. Sci.

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“…This performance requirement means that 32-bit microprocessors that can work with a 20 MHz or higher clock are needed instead of the conventional tiny processors near the threshold level working with a hundreds of kilo Hertz operational clock. To fulfill these requirements, a novel FD-SOI technique called silicon on thin buried oxide (SOTB) has been developed [1] and implemented on low power microprocessors [2], accelerators [3], and FPGAs [4].…”

Section: Introductionmentioning

confidence: 99%

“…Although a CPU with the SOTB was investigated in [2], it was not based on a performance and power model.…”

Section: Introductionmentioning

confidence: 99%

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara

Kitamori

et al. 2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Body bias control is an efficient means of balancing the trade-off between leakage power and performance especially for chips with silicon on thin buried oxide (SOTB), a type of FD-SOI technology. In this work, a method for finding the optimal combination of the supply voltage and body bias voltage to the core and memory is proposed and applied to a real micro-controller chip using SOTB CMOS technology. By obtaining several coefficients of equations for leakage power, switching power and operational frequency from the real chip measurements, the optimized voltage setting can be obtained for the target operational frequency. The power consumption lost by the error of optimization is 12.6% at maximum, and it can save at most 73.1% of power from the cases where only the body bias voltage is optimized. This method can be applied to the latest FD-SOI technologies.

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A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Cited by 18 publications

References 2 publications

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

Fully depleted SOI (FDSOI) technology

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

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