A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor

Kobayashi, Masaharu

doi:10.7567/apex.11.110101

Cited by 71 publications

(40 citation statements)

References 99 publications

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“…It has been found that when the capacitance parameters satisfy the condition | C i | > C c , a dielectric matching can be reached, and the hysteresis in the I DS – V GS curve is absent. [ 43 ] In other word, we need to break the dielectric matching effect to obtain a large‐enough hysteresis for high‐performance ferroelectric memories. Hence, confirming the dual‐gated coupling is required.…”

Section: Figurementioning

confidence: 99%

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

et al. 2020

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Ferroelectric field‐effect transistors (FeFETs) are one of the most interesting ferroelectric devices; however, they, usually suffer from low interface quality. The recently discovered 2D layered ferroelectric materials, combining with the advantages of van der Waals heterostructures (vdWHs), may be promising to fabricate high‐quality FeFETs with atomically thin thickness. Here, dual‐gated 2D ferroelectric vdWHs are constructed using MoS2, hexagonal boron nitride (h‐BN), and CuInP2S6 (CIPS), which act as a high‐performance nonvolatile memory and programmable rectifier. It is first noted that the insertion of h‐BN and dual‐gated coupling device configuration can significantly stabilize and effectively polarize ferroelectric CIPS. Through this design, the device shows a record‐high performance with a large memory window, large on/off ratio (107), ultralow programming state current (10−13 A), and long‐time endurance (104 s) as nonvolatile memory. As for programmable rectifier, a wide range of gate‐tunable rectification behavior is observed. Moreover, the device exhibits a large rectification ratio (3 × 105) with stable retention under the programming state. This demonstrates the promising potential of ferroelectric vdWHs for new multifunctional ferroelectric devices.

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Section: Figurementioning

confidence: 99%

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

et al. 2020

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“…For NEM‐FET, speed is limited to MHz due to the moving of heavy mass. Recently, negative capacitance (NC) effect in an FE/dielectric gate stack is proposed as a possible solution to break the 60 mV dec −1 limitation . HfO 2 ‐based FE materials are particularly attractive because of: 1) excellent CMOS‐compatibility by atomic layer deposition (ALD), 2) scalability to ultrathin thickness, 3) no sacrifice of I on , and 4) potential GHz operation…”

mentioning

confidence: 99%

Thickness‐Dependent Asymmetric Potential Landscape and Polarization Relaxation in Ferroelectric Hf_xZr₁₋_xO₂ Thin Films through Interfacial Bound Charges

Zhu

Ning

et al. 2019

Adv Elect Materials

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As complementary metal-oxide-semiconductor (CMOS) scaling down to sub-10 nm node, emerging technology to reduce power consumption enforced by shortchannel effects is actively pursued. [1] At single transistor level, the most effective way is to reduce operating voltage (V DD ) and subthreshold slope (SS). [2] However, SS in metal-oxide-semiconductor fieldeffect transistors (MOSFETs) is limited to 60 mV dec −1 at room temperature due to thermionic emission of carriers in the Boltzmann tail. To this end, novel concepts are proposed to design steep-slope transistors, including tunnel FET (TFET), [3] impact ionization MOS (IMOS), [4] and nanoelectromechanical FET (NEM-FET). [5] While achieving steep slope, these new device concepts sacrifice other aspects. TFETs utilize the band-to-band tunneling current and suffer from low on-state current. The IMOS needs very large bias voltage to drive impact ionization and has stability issues. For NEM-FET, speed is limited to MHz due to the moving of heavy mass. Recently, negative capacitance (NC) effect in an FE/dielectric gate stack is proposed as a possible solution to break the 60 mV dec −1 limitation. [6][7][8][9][10][11][12] HfO 2 -based FE materials are particularly attractive because of: 1) excellent CMOS-compatibility by atomic layer deposition (ALD), [13,14] 2) scalability to ultrathin thickness, [15] 3) no sacrifice of I on , [8] and 4) potential GHz operation. [16] In the original Landau-Ginzburg-Devonshire (LGD) theory, a ferroelectric below its Curie temperature is described by a doublewell free energy landscape. The two degenerate energy minima define two stable spontaneous polarization states, which can be programmed by the application of electric field. The minima of energy states are separated by a metastable region where the second-order differential of energy versus polarization is negative, defining a region of negative capacitance. [6] It has been proposed to stabilize the metastable negative capacitance region by serially adding a dielectric (DE) with parabolic energy landscape, the so-called capacitance matching. [17,18] The Landau-Khalatnikov (L-K) model shows that such quasistatic NC can theoretically give rise to sub-60 mV dec −1 switching without hysteresis in logic devices. [19] However, so far, the experimental observation of negative capacitance still cannot be fully explained by L-K model. The negative capacitance (NC) effect in ferroelectric materials provides a possible solution to break the Boltzmann tyranny and realize steep-slope field-effect transistors (FETs) with sub-60 mV dec −1 subthreshold slope (SS). HfO 2 -based ferroelectrics (FE) have attracted great attention as dielectric candidates for NCFETs due to their excellent scalability and compatibility with complementary metal-oxide-semiconductor technology. However, understanding of the ferroelectric properties of HfO 2 -based FEs, especially at reduced thickness, is still at an early stage. The quasistatic polarization relaxation behavior of ferroelectric Hf x Zr 1−x O 2 (HZO) thin fil...

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“…However, the leakage currents of transistors and memory have not been reduced at the same rate due to the fundamental thermionic limit, known as the Boltzmann Tyranny. [3,4] As a result, the heat generation and power consumption due to leakage current per chip become quite high, so that the development of ultralow-power semiconductor devices with reduced energy consumption is urgently required. [5] In particular, to enable low power operation of a field-effect transistor, it is necessary to control the channel surface potential (ψ s ) according to the gate voltage in order to minimize the leakage current in the weak inversion state.…”

Section: Doi: 101002/admi202001356mentioning

confidence: 99%

Compensation Charge Control and Modeling for Reproducing Negative Capacitance Effect of Hafnia Ferroelectric Thin Films

Ahn

Jung

Lee

et al. 2020

Adv Materials Inter

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To enable continuing development of the performance of highly integrated semiconductor chips, it is necessary to dramatically lower the power consumption of transistors. The discovery of the negative capacitance (NC) effect and the ferroelectric properties of HfO2 thin films have raised the possibility of surpassing the known physical limitations of the 60 mV subthreshold slope of the current MOSFETs. However, for commercial application, stable reproducibility of the voltage drop effect due to the ferroelectric polarization and a model that can fully interpret this phenomenon must be obtained. Despite intense recent efforts, guidance for the design of devices for mass production based on the NC effect is currently unavailable. This study has directly observed the NC effect and confirmed that the NC effect can be controlled through analysis based on the equivalent circuit theory. It is experimentally verified that the NC effect is caused by an imbalance between the amount of polarization switching and the amount of charge supplied to compensate for such switching in the initial stage of the applied voltage pulse. The results suggest that a gate structure or peripheral circuit that can actively respond to polarization switching is necessary to implement a novel MOSFET with breakthrough power consumption.

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A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor

Cited by 71 publications

References 99 publications

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

Thickness‐Dependent Asymmetric Potential Landscape and Polarization Relaxation in Ferroelectric Hf_xZr₁₋_xO₂ Thin Films through Interfacial Bound Charges

Compensation Charge Control and Modeling for Reproducing Negative Capacitance Effect of Hafnia Ferroelectric Thin Films

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A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor

Cited by 71 publications

References 99 publications

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

Gate‐Coupling‐Enabled Robust Hysteresis for Nonvolatile Memory and Programmable Rectifier in Van der Waals Ferroelectric Heterojunctions

Thickness‐Dependent Asymmetric Potential Landscape and Polarization Relaxation in Ferroelectric HfxZr1−xO2 Thin Films through Interfacial Bound Charges

Compensation Charge Control and Modeling for Reproducing Negative Capacitance Effect of Hafnia Ferroelectric Thin Films

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Thickness‐Dependent Asymmetric Potential Landscape and Polarization Relaxation in Ferroelectric Hf_xZr₁₋_xO₂ Thin Films through Interfacial Bound Charges