A physical lifetime prediction method for hot-carrier-stressed p-MOS transistors

Brox, M.; Wohlrab, E.; Weber, W.

doi:10.1109/iedm.1991.235341

Cited by 26 publications

(5 citation statements)

References 5 publications

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“…The simulation results agree closely with the experimental data. The parameter shift due to electron trapping in pMOS devices is known to have a linear time dependence on a semi-log plot [8,23]. A physical model for this dependence can be found in [23].…”

Section: Resultsmentioning

confidence: 99%

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TCAD-based simulation of hot-carrier degradation in p-channel mosfets using silicon energy-balance and oxide carrier-transport equations

Mukundan

Pagey

Cirba

et al. 1996

J. Technol. Comput. Aided Des. TCAD

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We present a TCAD-based approach for characterizing hot-carrier degradation in p-channel MOSFETs that includes models for hot-electron injection, carrier transport, and electron trapping in the oxide. The energy-balance equations have been solved in the silicon substrate to accurately model the carrier-heating and injection processes. This approach clearly illustrates the physical mechanisms responsible for hot-carrier degradation in p-channel MOSFETs. The simulations have been compared with experimental data obtained from 0.8μm SOI pMOS devices and show an excellent match.

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Section: Resultsmentioning

confidence: 99%

“…Several semi-empirical models derived from the lucky-electron injection theory have been proposed that predict the time-dependence of hot-carrier-induced device parameter shifts [6,7,8]. However, these models utilize technology-dependent fitting parameters and do not capture the underlying physical mechanisms.…”

Section: Introductionmentioning

confidence: 99%

TCAD-based simulation of hot-carrier degradation in p-channel mosfets using silicon energy-balance and oxide carrier-transport equations

Mukundan

Pagey

Cirba

et al. 1996

J. Technol. Comput. Aided Des. TCAD

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“…It was demonstrated by Brox et a f [5] that trapped electrons in a gate oxide can be released by applying a high electric field across the oxide. They observed a partial recovery of device characteristics of a stressed device.…”

Section: 3mentioning

confidence: 98%

The hot-carrier induced degradation mechanisms of 0.8 mu m LDD p-MOSFET with 850 degrees C wet gate oxidation

Pan

1993

31st Annual Proceedings Reliability Physics 1993

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10 Kent Ridge Crescent, Singapore 0511, Fax: (65)-7791103. AbstractThe hot-carrier induced degradation mechanisms of LDD p-MOSFET's have been investigated. Gate oxide layers were grown in a wet ambient at 850°C' which was reported as an advantageous candidate for a 0.8pm process [l]. Degradation of the saturation drain current proceeds logarithmically in stress time while that of the linear current saturates. In addition to the trapping of electrons in gate oxide layers, donor-like interface states were generated by the hot carrier injection. The presence of the interface states was verified by measuring the degradation of the linear current and the threshold voltage after trapped electrons in the gate oxide are fully released. The interface state densities were estimated by fitting the calculated drain current degradation to the measured one by using two dimensional process and device simulators.

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“…The exponential decrease of the electron injection current leads to a region of occupied electron traps expanding logarithmically over time from the drain towards the direction of the source [8]. x edge , defined as the length of the region which is saturated with the trapped electrons, can be expressed as [14] x edge (t) = x 0 ln j 0 q σ t (4)…”

Section: Analytical Model For the Pmosfet's Subthreshold Current Degr...mentioning

confidence: 99%

Modelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing

Qin¹,

Chim²,

Chan³

et al. 1998

Semicond. Sci. Technol.

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Hot-carrier injection is observed increasingly to degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier-stressed submicrometre channel length devices. The channel length reduction is subsequently extracted. An empirical relationship is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this relationship, we can determine the device lifetime or predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology. The degradation of the PMOSFET subthreshold current, which imposes a major limit on device reliability for deep-submicron technology and low-power applications, is fully described by a physical analytical model.

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A physical lifetime prediction method for hot-carrier-stressed p-MOS transistors

Cited by 26 publications

References 5 publications

TCAD-based simulation of hot-carrier degradation in p-channel mosfets using silicon energy-balance and oxide carrier-transport equations

TCAD-based simulation of hot-carrier degradation in p-channel mosfets using silicon energy-balance and oxide carrier-transport equations

The hot-carrier induced degradation mechanisms of 0.8 mu m LDD p-MOSFET with 850 degrees C wet gate oxidation

Modelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing

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