Statistical intra-die variations of device parameters from a 0.5 pm CMOS process are determined, finding good agreement with the (WLY'" model. It is proven that channel doping variations are responsible. Additionally, systematic proximity-induced parameter deviations due to different field oxide surroundings are found. The resulting variations of inverter delays for different supply voltages and gate areas are determined.

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Based on the Neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS -based logic applications.