A physics-based model for the avalanche ruggedness of power diodes

Hurkx, G.A.M.; Koper, N.

doi:10.1109/ispsd.1999.764089

Cited by 9 publications

(4 citation statements)

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“…In this case, E AV remains below the critical value showing premature failure. In addition, this work shows that failure is not due to the displacement current as proposed in [12] or due to dV BR /dT as is the case in power diodes [13]. Displacement current caused latching failure at switching only above ≈ 105 A in DUTs in this work.…”

Section: Discussionmentioning

confidence: 48%

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Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

Nida

Kakarla

Ziemann

et al. 2021

IEEE Trans. Electron Devices

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The phenomenon of reduced energy capability of power metal-oxide-semiconductor fieldeffect transistors (MOSFETs) at high avalanche currents is investigated in commercial 1.2-kV 4H-SiC MOSFETs. Unclamped inductive switching (UIS) measurements as well as electrical transport simulations are used to identify the current paths and maximum avalanche currents, providing insight into the design limits. The investigated devices show a reduced energy capability for avalanche current above 52 A due to the latching of the parasitic bipolar junction transistor (BJT). The BJT also limits the maximum switchable current to ≤102 A. Based on the measurements and simulations, a procedure utilizing UIS measurements for identification of design limits is presented.

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Section: Discussionmentioning

confidence: 48%

“…Thus, avalanche current capability tests can be used as feedback for the design and optimization of robust devices. For such purposes, analytical models for simpler structures of silicon power diodes were developed [13]. However, reliable models for three-terminal devices are still not available.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

Nida

Kakarla

Ziemann

et al. 2021

IEEE Trans. Electron Devices

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“…The simulator solves all the semiconductor equations numerically within the 2-D structure grid using a finite element method. Initially, E = 1/2 * L* (I peak ) 2 of energy is stored in the inductor from the drain current flowing when the FET is on (1,5). This energy generates a voltage due to back emf that exceeds the drain-source breakdown voltage when the power is turned off, causing avalanche breakdown in the MOSFET.…”

Section: Device Structure and Simulation Test Set-upmentioning

confidence: 99%

Effect of Finger and Device-Width on Ruggedness of nLDMOS Device under Single-Pulse Unclamped Inductive Switching (UIS) Conditions

Agarwal

Sharma²,

Tsai

et al. 2012

ECS Trans.

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This work demonstrates the effect of increasing finger number and width on the ruggedness of the nLDMOS device under test (DUT). The ruggedness or energy handling capability is analyzed by twodimensional (2-D) and three dimensional (3-D) device and circuit simulations. The set failure criterion in our study and simulation is the device temperature reaching a critical value equal to the melting point of metal-contacts. The maximum energy is calculated by considering the pass-case prior to device failure and time-integrating the drain voltage and current for the avalanche duration. Maximum avalanche energy handling capability is seen to be increased linearly with number of device fingers. UIS test was also performed on width extended multi-finger nLDMOS device structures. The simulated results provided useful approaches to predict real experimental results and contribute to their physical interpretation by identification of the mechanism of device-failure, hot-spot location and continuous temperature extraction.

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“…This is the ability to withstand high current transients under avalanche breakdown conditions. Since Is (saturation current) is the maximum peak current at which an LDMOS can sustain before failure, the corresponding energy can be expressed by Emax (=Is 2 *L/2) [1]. In general, the value of Emax is a parameter measuring avalanche ruggedness and one of the most important parameters that affects avalanche ruggedness appears to be layout type.…”

Section: Introductionmentioning

confidence: 99%

Analysis on the Avalanche Ruggedness of Finger Type and Stripe Type LDMOS Transistor

Kwon¹,

Choi²,

Kim³

et al. 2000

30th European Solid-State Device Research Conference

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In order to investigate how to change avalanche ruggedness according to layout type in LDMOS, the two types of structure such as finger type and stripe type were investigated. The difference of the avalanche ruggedness is due to inductor voltage difference caused by body-pinch resistance and the inductor voltage difference affects the ratio of Emax (reverse maximum holding energy of device) variation to load inductance (L) variation (= Emax / L). In this paper, we describe in detail how to optimize the layout type of LDMOS according to their load inductance (L).

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A physics-based model for the avalanche ruggedness of power diodes

Cited by 9 publications

References 0 publications

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

Analysis of Current Capability of SiC Power MOSFETs Under Avalanche Conditions

Effect of Finger and Device-Width on Ruggedness of nLDMOS Device under Single-Pulse Unclamped Inductive Switching (UIS) Conditions

Analysis on the Avalanche Ruggedness of Finger Type and Stripe Type LDMOS Transistor

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