A pipelined FFT processor for word-sequential data

Bi, Guoan; Jones, E.V.

doi:10.1109/29.45545

Cited by 163 publications

(91 citation statements)

References 2 publications

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“…This criterion shows the lowest area and the highest performance that each architecture can obtain. As it can be observed in the table, feedback (FB) architectures and some feedforward (FF) ones [5], [7] require less hardware components and achieve a throughput of one sample per clock cycle. On the other hand, the parallelization of feedforward architectures has the advantage of a higher throughput and a lower latency due to an increase in area.…”

Section: Comparison To Other Algorithms For the Computation Of Thementioning

confidence: 99%

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A Pipelined FFT Architecture for Real-Valued Signals

Garrido

Parhi

Grajal

2009

IEEE Trans. Circuits Syst. I

121

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Abstract-This paper presents a new pipelined hardware architecture for the computation of the real-valued fast Fourier transform (RFFT). The proposed architecture takes advantage of the reduced number of operations of the RFFT with respect to the complex fast Fourier transform (CFFT), and requires less area while achieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computation of the RFFT, which, contrary to previous approaches, presents a regular geometry suitable for the implementation of hardware structures. Moreover, the algorithm can be used for both the Decimation In Time (DIT) and Decimation In Frequency (DIF) decompositions of the RFFT and requires the lowest number of operations reported for radix 2.Finally, as in previous works, when calculating the RFFT the output samples are obtained in a different order. The problem of reordering these samples is solved in this paper and a pipelined circuit that performs this reordering is proposed.

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Section: Comparison To Other Algorithms For the Computation Of Thementioning

confidence: 99%

“…According to the input order of the data, the upper butterfly of the structure computes the pairs of samples (0, 8), (1,9), (2,10) and (3,11), whereas the lower butterfly operates samples (4, 12), (5, 13), (6,14) and (7,15).…”

Section: Comparison To Other Algorithms For the Computation Of Thementioning

confidence: 99%

A Pipelined FFT Architecture for Real-Valued Signals

Garrido

Parhi

Grajal

2009

IEEE Trans. Circuits Syst. I

121

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“…Radix-x Cooley-Tukey algorithm is one of the most popular algorithms for hardware implementation [3,4,5,6]. Most hardware solutions for Radix-x FFT fall into the following categories: delay feedback or delay commutator architectures [4], such as Radix-2 2 single-path delay feedback FFT [4], Radix-4 single-path delay commutator FFT [5], etc. By focusing on circuit level optimizations, these solutions achieved improvement either in throughput, area, or power.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient parameterized FFT architecture

Ren

Prasanna

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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Recently, there has been a growing interest within the research community to improve energy efficiency. In this paper, we revisit the classic Fast Fourier Transform (FFT) for energy efficient designs on FPGAs. Parameterized FFT architecture is proposed to identify design trade-offs in achieving energy efficiency. We first perform design space exploration by varying the algorithm mapping parameters, such as the degree of vertical and horizontal parallelism, that characterize the decomposition based FFT algorithms. After empirical selection on the values of algorithm mapping parameters, an energy-performance-area trade-off design for energy efficiency is identified by varying the architecture parameters, including the type of memory elements, the type of interconnection network and the number of pipeline stages. The tradeoffs between energy, area, and time are analyzed using two performance metrics: the Energy×Area×Time (EAT) composite metric and the energy efficiency (defined as the number of operations per Joule). From the experimental results, a design space is generated to demonstrate the effect of these parameters on the various performance metrics. For N -point FFT (16 ≤ N ≤ 1024), our designs achieve up to 28% and 38% improvement in the energy efficiency and EAT, respectively, compared with a state-of-the-art design.

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“…The R4SDC was proposed by Bi and Jones [3] and uses an iterative architecture to calculate the radix-4 FFT. The key to the algorithm is splitting the FFT into different stages by using different radices.…”

Section: R4sdc Architecturementioning

confidence: 99%

“…Pipeline FFT architectures have been studied since the 1970's when real-time large scale signal processing requirements became prevalent. Several different architectures have been proposed, based on different decomposition methods, such as the Radix-2 Multipath Delay Commutator (R2MDC) [1], Radix-2 Single-Path Delay Feedback (R2SDF) [2], Radix-4 Single-Path Delay Commutator (R4SDC) [3], and Radix-2 2 Single-Path Delay Feedback (R2 2 SDF) [4]. More recently, Radix-2 2 to Radix-2 4 SDF FFTs were studied and compared in [5]; in [6] an R2 3 SDF was implemented and shown to be area efficient for 2 or 3 multipath channels.…”

Section: Introductionmentioning

confidence: 99%

Pipeline FFT Architectures Optimized for FPGAs

Zhou

Peng

Hwang

2009

International Journal of Reconfigurable Computing

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This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R2 2 SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0.034 Msamples/s/slice. The R4SDC architecture ran at 123.8 MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0.028 Msamples/s/slice. On Virtex-4, the 16-bit 1024-point R2 2 SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 219.2 MHz and used 3064 slices, giving a 0.072 Msamples/s/slice ratio. The R2 2 SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme. This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors.

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A pipelined FFT processor for word-sequential data

Cited by 163 publications

References 2 publications

A Pipelined FFT Architecture for Real-Valued Signals

A Pipelined FFT Architecture for Real-Valued Signals

Energy efficient parameterized FFT architecture

Pipeline FFT Architectures Optimized for FPGAs

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