A portable digital DLL for high-speed CMOS interface circuits

Garlepp, B.W.; Donnelly, Kevin; Kim, Jun; Chau, P.S.; Zerbe, J.; Huang, Ching-Chao; Tran, Chanh; Portmann, C.; Stark, D.; Chan, Yiu-Fai; Lee, T.H.; Horowitz, Mark

doi:10.1109/4.760373

Cited by 171 publications

(58 citation statements)

References 13 publications

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“…It is difficult to hold the clock duty cycle at its ideal value 50%, irregularity in signal and variation (P and N MOS) in the long buffer. So the clock duty cycle deviates, the clock pulse may vanish inside the clock buffer, width becomes Shorten or lengthy (Garlepp et al, 1999).…”

Section: Methodsmentioning

confidence: 99%

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High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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Problem statement:In any multimedia processor, controller may consume most of the onchip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications are made with software reference implementation. The whole system is implemented in 0.18 µm CMOS technology, where an input reference clock to an outgoing data clock monitors and true locking is initialized with 50% duty cycle correction. Results: From the measurement result of DLL operation, the output clock jitter is analyzed. Power consumption of DLL including large size output buffer is about few mW. Conclusion: The great challenge in this implementation is communication bandwidth, has brought to process variation and power state reduction techniques. In addition, inefficiency of computing capacity and simultaneous switching noise is reduced in the real time applications.

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Section: Methodsmentioning

confidence: 99%

“…This increase effectively shrinks the data valid window (t DQV ) and makes the system more subject to timing errors. In a Very Large Scale Integrated (VLSI) circuit design, it is advantageous to use a digital DLL design (Garlepp et al, 1999), for its portability across process nodes.…”

Section: Introductionmentioning

confidence: 99%

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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“…In DLL, VCDL is used in place of VCO which makes it differ from PLL. If frequency multiplier operation is not needed then a DLL is preferred over PLL because of high stability, less locking time and no jitter accumulation [2], [3]. DLL has a wide number of applications such as clock generators in DRAM ICs, microprocessors, clock de-skewing circuits [4], [5].…”

Section: Introductionmentioning

confidence: 99%

250 MHz Multiphase Delay Locked Loop for Low Power Applications

Suman¹,

Sharma²,

Ghosh³

2017

IJECE

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Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. [5]. Locking time, lock range and jitter performance, static phase error, low power consumption and immunity against process voltage temperature loading (PVTL) variations are the most important metrics of a DLL. A DLL can be realized by a number of architectures; analog and digital DLLs are the two most important types among them [6]. Analog DLLs have better performance in terms of jitter, layout area, power supply rejection ratio, power consumption and clock skew. This paper introduces a mixed mode DLL in which single ended differential pair based VCDL is used which provides high stability against temperature and power supply variations. The proposed circuit depicts superior performance in terms of speed, power consumption, and locking range. The organization of remaning four sections are starting with architecture of basic DLL followed by analysis of different blocks, simulation results and conclusion.

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“…1 (d), shows high phase-resolution, less dependance on process variation and higher tunability range. When the circuit described in [3] was used multiple times, 8 clock phases could be generated from an original clock, as shown in Fig. 1 (a).…”

Section: Proposed Architecturementioning

confidence: 99%

“…The 8 phases of the clock are generated using a PI circuit that takes two clocks as an input and generate a third that has a phase between the original two clocks. The PI circuit detailed in [3], and shown in Fig. 1 (d), shows high phase-resolution, less dependance on process variation and higher tunability range.…”

Section: Proposed Architecturementioning

confidence: 99%

All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS

Bushnaq

Ikeda

Asada

2012

IEICE Electron. Express

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Abstract:In this paper, an all-digital Power Amplifier (PA) that is tunable and fully-integrated on chip using 0.18 µm CMOS is presented. The PA is designed using all-digital output-connected inverters controlled by a multi-phase clock generated using a multi-stage phase interpolator. Experimentally, in addition to the advantage of being alldigital and tunable, the PA consumed around 0.03 mW/MHz, which is less than power consumed in recently proposed designs.

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A portable digital DLL for high-speed CMOS interface circuits

Cited by 171 publications

References 13 publications

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

250 MHz Multiphase Delay Locked Loop for Low Power Applications

All-digital tunable power amplifier consuming 0.03mW/MHz using 0.18µm CMOS

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