A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

Abstract

A mechanism is proposed for reconciling an observed large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET. Dopant in the source-drain extension is assumed to segregate to the Si/SiO 2 interface by a reversible reaction. It then diffuses along the interface into the channel region where the dopant is able to return to the bulk Si. By this means a shallow sliver of p-type dopant is formed which protrudes laterally from the source-drain extension into the channel. Simulations with this model are found to match measured PFET device parameters where other assumptions fail.

A CMOS-Compatible Rapid Vapor-Phase Doping Process for CMOS Scaling

“…The dependence of the overlap capacitance on is stronger in pMOSFETs than in nMOSFETs due to the interfacial diffusion of boron underneath the gate edge. Similar results have been reported by Young et al [13] who considered that boron is easy to diffuse along the interface into the channel region.…”