A Power Cloud System (PCS) for High Efficiency and Enhanced Transient Response in SoC

Shih, Chun-Jen; Chu, K.R.; Lee, Yu-Huei; Chen, Wei‐Chung; Luo, Hsin-Yu; Chen, Ke-Horng

doi:10.1109/tpel.2012.2207917

Cited by 14 publications

(3 citation statements)

References 23 publications

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“…In designing a supply modulator for power amplifiers [25,26] , it is required that the DC-DC converter and the linear regulator should work all the time to achieve fast responses and small output ripples, but the efficiency is de- New compensator Previous compensator graded and the loop compensation becomes complicated. When employing the hybrid scheme to improve transient responses of DC-DC converters, it is essential that the linear regulators are deactivated in the steady state to eliminate quiescent consumption.…”

Section: Design Challenges Of Hybrid Schemementioning

confidence: 99%

“…It consists of the parallel operation of the DC-DC converter and a linear regulator. This is a common scheme in designing the supply modulator of a power amplifier [25,26] , and has been employed to im-prove transient responses [27][28][29][30][31] . It is essential that the linear regulator should only be activated during load transients and is completely deactivated in the steady state such that efficiency is not compromised.…”

Section: Introductionmentioning

confidence: 99%

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Fast-transient techniques for high-frequency DC–DC converters

Cheng

Tang

et al. 2020

J. Semicond.

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A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented. An improved differential difference amplifier (DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients, and to achieve near-optimal transient responses with simple PWM control only. Moreover, a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses. By monitoring the output voltage of the compensator instead of the output voltage of the converter, the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop. The converter was fabricated in a 0.13 μm standard CMOS process using 3.3 V devices. With an input voltage of 3.3 V, the measured peak efficiencies at the output voltages of 2.4, 1.8, and 1.2 V are 90.7%, 88%, and 83.6%, respectively. With a load step of 1.25 A and rise and fall times of 2 ns, the measured 1% settling times were 220 and 230 ns, with undershoot and overshoot with PWM control of 72 and 76 mV, respectively. They were further reduced to 36 and 38 mV by using the proposed hybrid scheme, and 1% settling times were also reduced to 125 ns.

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Section: Design Challenges Of Hybrid Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fast-transient techniques for high-frequency DC–DC converters

Cheng

Tang

et al. 2020

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…T ODAY'S system-on-chip (SoC) applications are targeted to integrate a complex system in a low form factor and cost [1]- [3]. The power management of such an application is also very critical and requires higher level of system integrity without compromising the transient response [4]- [6] and increasing the quiescent current [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Analysis, Design, and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-Less Low Dropout Regulator

Maity

Patra²

2016

IEEE Trans. Power Electron.

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Dynamically slew enhanced adaptive bias (DSE-AB) scheme has been recently introduced for an externally compensated (with-capacitor) regulator for achieving a very fast transient response. The combined effects of enhanced slew rate and expanded loop bandwidth using the DSE-AB scheme produce a very low undershoot and overshoot. When this scheme is directly applied to an internally compensated, capacitor-less low dropout regulator (CL-LDR) topology, besides the slew enhancement, the instantaneous dynamic current may reduce the damping factor momentarily and produce more ringing in the load transient response. This paper first analyzes the generation of momentary low damping factor in the CL-LDR that uses the DSE-AB scheme. A current limited DSE-AB scheme is also proposed to increase the momentary damping factor for minimizing the ringing in the settling behavior. To validate the proposed scheme, the CL-LDR is implemented in a 0.18 µm CMOS technology and the regulator's performance is evaluated in different dynamic conditions. Experimental result shows an undershoot of 45 mV during 0-100 mA load step and an overshoot of 25 mV during the other edge.Index Terms-Low dropout regulator, capacitor-less regulator, damping factor, main feedback loop, adaptive bias loop.

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Ripple‐Based Control Technique Part II

2016

Power Management Techniques for Integrated Circuit Design

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A Power Cloud System (PCS) for High Efficiency and Enhanced Transient Response in SoC

Cited by 14 publications

References 23 publications

Fast-transient techniques for high-frequency DC–DC converters

Fast-transient techniques for high-frequency DC–DC converters

Analysis, Design, and Performance Evaluation of a Dynamically Slew Enhanced Adaptively Biased Capacitor-Less Low Dropout Regulator

Ripple‐Based Control Technique Part II

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