A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

Abstract

A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the test set adopts a series of preprocessed strategies including don't care bit based 2-D adjusting, Hamming Distance based 2-D reordering and test cube matrix based two transpose, all steps will be orderly executed in interspersed way. The six largest ISCAS'89 benchmark circuits verify the proposed method. Experimental results show that the switching activities are effectively reduced when the test set is loaded for on-chip scan testing. ASDFR with MT-filling scheme ensures high compression ratio, the scan-in test power dissipation is further decreased by don't care bit based 2-D adjusting and Hamming Distance 2-D reordering. In addition, the BIST TPG method with less test application time and smaller algorithm complexity can be widely applied to actual chip design without adding extra decoder area overhead.

Compressive Sensing Measurement Matrix Generator Based on Improved SC-Array LDPC Code

“…Next, the digital outputs are obtained from the analog outputs using analog-to-digital (ADC) sampling. Compared with conventional compression methods [12], this analog implementation of compressive sensing entails lower quantized noise as it converts the input signal to digital codes before compression [13,14].…”

Double Hamming distance‐based 2D reordering method for scan‐in power reduction and test pattern compression

“…Therefore, it is not only necessary to decrease the logic state transitions within a single test pattern, but also to reduce those between two consecutive test patterns. To this end, some researchers have proposed different 2D reordering methods [7,8]. These methods reorder the rows and columns of the test set separately to make the consecutive rows or columns in the test set as similar as possible.…”

“…The second Hamming distances between the three vectors v c , v j and v i are calculated by (8). If they satisfy the following inequality:…”

“…To show the effectiveness of our method, we take the test set S = (Q 1 , Q 2 , Q 3 , Q 4 ) in [8] as an example. The four test patterns are listed as follows:…”

“…The peak and the average power consumptions are estimated to be 28 and 12.25, respectively, whereas those for the 2D reordered test set are 8 and 4.75, respectively. Another power consumption result for the original test was mentioned in [8], where Yuan et al used the reordering method proposed by themselves to derive the following test set:…”