A power modeling and characterization method for the CMOS standard cell library

Lin, Jian Hung; Shen, Wei; Jou, Jing-Yang

doi:10.1109/iccad.1996.569828

Cited by 4 publications

(2 citation statements)

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“…Absolute error is defined as the difference between the values that are examined (10). Relative error is defined as the ratio of the previous determined error (absolute error) and the characterized value (11)…”

Section: Cell's Level Validationmentioning

confidence: 99%

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New voltage and temperature scalable gate delay model applied to a 14nm technology

Charafeddine

Ouardi

2020

IJEECS

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<p>The following work shows an innovative approach to model the timing of standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work, characterization of cells of a standard cell library is done in an hour whereas it is done in 650 hours with the classical method. Also, a method for validating and verification of the precision of the modelled data is presented by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.</p>

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Section: Cell's Level Validationmentioning

confidence: 99%

“…A number of characterization methodologies were proposed by many researchers in the aim of increasing the precision of the models ignoring the large simulation time [10][11][12][13]. In his paper J. Jianhua et al state that the choice of input parametes (index1, index2) in the timing LUT impacts the accuracy [10].…”

Section: Introductionmentioning

confidence: 99%