A power optimized 14-bit SC ΔΣ modulator for ADSL CO applications

Abstract

Digital subscriber line (DSL) applications require high resolution and wide bandwidth A/D converters. The dynamic range requirement typically results in 14-bits and 13-bits over an analog signal bandwidth of 300kHz and 1.1MHz, respectively. A robust and low-cost design is necessary since the ADC is targeted for high volume production. Therefore, an SC modulator was chosen instead of a time-continuous approach. As far as is known to the authors, the achieved power efficiency (8mW) is the best compared to similar SC converters reported in the open literature. To not compromise the maximum data rate, the harmonic distortion may not exceed -80dBc for a -6dB full-scale sinusoidal test signal.

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

“…To demonstrate the validity of removing DAC linearization (DEM) in the main DAC, three 3 rd order Ms are simulated using the MATLAB/Simulink ® model [11], [12] under various conditions: one analog feed-forward M [7] as a reference and two digital feed-forward Ms as illustrated in Fig. 6, one with a 4b auxiliary quantizer and the other with a 5b auxiliary quantizer.…”

“…To relax power consumption requirement, one can use the feed-forward technique in the analog [7], [8] or in the digital domain [9], [10]. As a result, the OpAmps are virtually independent from the input signal and process only the quantization noise.…”

“…Reference [7] and [8], however, have a tight timing specification for operating the DEM algorithm as shown in Fig. 2: The input signal X should be summed with the output of the 2 nd integrator V 2 , and the summed result should be resolved during phase 1 (P 1 ) to have a proper settling or charge distribution, depending on the type of analog adder used.…”

“…Figs. 1 and 2 illustrate a conventional wideband M [7] and a timing diagram related to the DEM operation, respectively. Ideally, the DEM algorithm can be processed before the DAC operation completes, but it burdens the first stage OpAmp in the modulator.…”

Low-Voltage, Low-Power Basic Circuits

“…In addition, in the case of a small mismatch between the two parallel paths, mismatch energy could be present around Fs/2 [28]. [29], [4]) Another possible approach to reduce power consumption has been applied to modulator. It based on the concept that the power consumption depends also on the signal amplitude (slew-rate, etc…).…”