The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm2, which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

The ADC shown in this paper uses an innovative Sigma-Delta (61) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-61 ADC prototype has been fabricated in 0.13 m CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr 2 BW 2 ENOB ) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm 2 .

Digital subscriber line (DSL) applications require high resolution and wide bandwidth A/D converters. The dynamic range requirement typically results in 14-bits and 13-bits over an analog signal bandwidth of 300kHz and 1.1MHz, respectively. A robust and low-cost design is necessary since the ADC is targeted for high volume production. Therefore, an SC modulator was chosen instead of a time-continuous approach. As far as is known to the authors, the achieved power efficiency (8mW) is the best compared to similar SC converters reported in the open literature. To not compromise the maximum data rate, the harmonic distortion may not exceed -80dBc for a -6dB full-scale sinusoidal test signal.

No abstract

No abstract