The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm2, which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

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The high-resolution and low power consumption ADCs demand in read-out circuits for biopotential systems has been increased in the last few years. This paper presents a new architecture to implement this kind of ADC´s using multistage time encoding converters. Due to the low voltage supply and low power demanded on this type of applications, the proposed ADC is formed by a second-order multibit noise-shaping converter using a time domain integrating quantizer as first stage and a Differential Gated-Ring Oscillator (DGRO) as second stage of the multistage architecture (MASH). The first-order noise shaping behavior of the DGRO allows to obtain a total third order noise shaping performance in the final ADC output. Moreover, using the arrangement proposed in this work, the low power requirements demanded in biopotential read-out circuits can be achieved. This because the multi-bit flash quantizer used in standard noise-shaping ADCs has been replaced by a time domain integrating quantizer that uses a one bit comparator and a PWM DAC. In addition the second stage of the MASH structure is used to quantize the width of a digital pulse with the benefit of first order noise shaping. Hence, the combination of a GRO with an integrating quantizer may produce a hardwareefficient multistage ADC (MASH) due to the digital nature of the GRO. As an example, the transistor level performance of a MASH 2-1 ADC with the proposed architecture has been evaluated. The transistor level simulations show that the ADC can achieve an ENOB = 15bits in a signal bandwidth of 16kHz using a 0.18μm CMOS technology at 1.2V.

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