A 0.1 mm$^{2}$, Wide Bandwidth Continuous-Time $\Sigma\Delta$ ADC Based on a Time Encoding Quantizer in 0.13 $\mu$m CMOS

Abstract

The ADC shown in this paper uses an innovative Sigma-Delta (61) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-61 ADC prototype has been fabricated in 0.13 m CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr 2 BW 2 ENOB ) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm 2 .

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

“…Several researchers have noticed these advantages, and severall SOSDM designs have been published ( [7,10,12,13]). However, despite this interest, the SOSDM system still remains a research topic, and several aspects of the SOSDM have not sufficiently been analyzed.…”

“…Practical systems may use higher order loop filters. However, these filters are often designed to have approximately first order roll-off at high frequency ( [7]- [10,12,13]), such that even for such high-order systems, the following analysis remains approximately valid.…”

A Rigorous Approach to the Robust Design of Continuous-Time $\Sigma\Delta$ Modulators

“…Moreover this parasitic loop delay is sensitive to process-voltage-temperature (PVT) variations. In a design with up to GHz clock frequency [1], [14] its nominal value may well be as high as 10 % of the sampling period, with a variation of 50 %. Formally this leads to:…”

“…[7] can be used in our approach, but these were found to be too conservative. Equation (14) indicates that, a more aggressive NTF will have a higher risk for quantizer overloading and thus a lower MSA.…”

A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

“…IN recent years, continuous time (CT) sigma delta modulators have attracted increasingly due to low power consumption, low supply voltage, high sampling frequency and high bandwidth in comparison with similar discrete time sigma delta modulators [1][2][3]. Moreover, because of placing sampler inside loop filter, charge injection effect and nonlinear sampling switched on resistances are significantly suppressed.…”