A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications

Pavan, Shanthi; Krishnapura, Nagendra; Pandarinathan, Ramalingam; Sankar, Prabu

doi:10.1109/jssc.2007.914263

Cited by 116 publications

(67 citation statements)

References 13 publications

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“…Compared to the current-steering DAC, the resistive DAC has less thermal noise [5]. Each unit element is formed by two parts: a D-flip-flop updates one sample at the clock edge, and the resistor converts the DAC reference voltage into the unit current [17]. The output of all the unit elements are connected together, which performs current summation of all the unit currents.…”

Section: Dacmentioning

confidence: 99%

A continuous-time delta-sigma ADC with integrated digital background calibration

Tan

Miao

Palm

et al. 2016

Analog Integr Circ Sig Process

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This work presents a digital calibration technique in continuous-time (CT) delta-sigma (DR) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT DR converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

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Section: Dacmentioning

confidence: 99%

A continuous-time delta-sigma ADC with integrated digital background calibration

Tan

Miao

Palm

et al. 2016

Analog Integr Circ Sig Process

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“…In addition, the large integrating capacitor in INT 11 (due to a small scaling coefficient c 1 ) loads the amplifier significantly and requires a large current drive capability. A Class-A/Class-AB configuration with two independent common-mode feedback (CMFB) loops is used to implement the first amplifier [6]. According to Table II, specifications are found much relaxed for the amplifiers in a later active block.…”

Section: Design Strategymentioning

confidence: 99%

Design considerations for pipelined continuous-time incremental Sigma-Delta ADCs

Tao

Chi

Rusu

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper addresses design considerations for power-efficient pipelined continuous-time (CT) incremental Sigma-Delta (IΣ∆) ADC architectures. By pipelining identical CT IΣ∆ ADC stages, the proposed architecture provides the design freedom coming from both the pipeline ADC and the IΣ∆ ADC. In searching for a low-power solution given a target resolution, different configurations are examined analytically and simulated using behavioral models. For further power reduction, power-efficient circuits are proposed to implement the active blocks in each configuration. Based on the architecture-level analysis, a configuration that leads to minimum power-area consumption is chosen and implemented as a test-case using the proposed circuit blocks. Post-layout simulations show that the test-case ADC, with 3.2-kHz bandwidth, achieves a peak SNDR of 82.5-dB while dissipating a total power of 18.27-µW.

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“…The ΔΣ ADC is also proven to be well suitable for low-bandwidth signal conversion by employing oversampling, and is robust to device mismatches in the forward signal path when using nano-CMOS processes [5][6][7]. Traditionally, discrete-time (DT) ΔΣ ADC were the commonly used ΔΣ architecture.…”

Section: Open Accessmentioning

confidence: 99%

“…Many such modulators have been reported over previous decades [8,9]. However, in recent years, the continuous-time delta-sigma (CT-ΔΣ) ADC is being preferred in low-power signal-processing applications due to several attractive features like an inherent anti-aliasing filter (AAF), relaxed bandwidth requirements of the active elements and lower power consumption when compared to their discrete-time counterparts [3,5,7].…”

Section: Open Accessmentioning

confidence: 99%

“…This can be used to our benefit by scaling down the integrator performance requirements from the first to the last integrator resulting in an overall reduction in modulator power consumption. An active-RC topology is chosen for the loop filter because of its high linearity and low noise characteristics [3,5,7,10]. Since the first integrator sets the input referred noise and distortion for the overall modulator, the performance requirements from the first opamp are higher than the rest of the opamps [10,13].…”

Section: Choice Of Loop Filter Architecturementioning

confidence: 99%

See 1 more Smart Citation

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

Balagopal

Saxena

2012

JLPEA

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A third-order single-bit CT-ΔΣ modulator for generic biomedical applications is implemented in a 0.15 µm FDSOI CMOS process. The overall power efficiency is attained by employing a single-bit ΔΣ and a subthreshold FDSOI process. The loop-filter coefficients are determined using a systematic design centering approach by accounting for the integrator non-idealities. The single-bit CT-ΔΣ modulator consumes 110 µW power from a 1.5 V power supply when clocked at 6.144 MHz. The simulation results for the modulator exhibit a dynamic range of 94.4 dB and peak SNDR of 92.4 dB for 6 kHz signal bandwidth. The figure of merit (FoM) for the third-order, single-bit CT-ΔΣ modulator is 0.271 pJ/level.

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A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications

Cited by 116 publications

References 13 publications

A continuous-time delta-sigma ADC with integrated digital background calibration

A continuous-time delta-sigma ADC with integrated digital background calibration

Design considerations for pipelined continuous-time incremental Sigma-Delta ADCs

A Low-Power Single-Bit Continuous-Time ΔΣ Converter with 92.5 dB Dynamic Range for Biomedical Applications

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