A practical gate resizing technique considering glitch reduction for low power design

Abstract

We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. The effect of our method is verified experimentally using 8 benchmark circuits with a 0.6 m standard cell library. Our method reduces the power dissipation from the minimum-sized circuits further by 9.8% on average and 23.0% maximum. We also verify that our method is effective under manufacturing variation.

Optimal V/sub th/ assignment and buffer insertion for simultaneous leakage and glitch minimization though integer linear programming (ILP)

“…However, with the recent trends in CMOS technology scaling, leakage power is rapidly increasing to become the dominant source of power consumption [2]. Further, as power due to the spurious signal transition (glitch power) that does not contribute to the circuit functionality occupy around 20%-40% of the total power dissipated, it becomes necessary to minimize glitches too along with leakage power [3].…”

A Review on Glitch Reduction Techniques

“…) P Total = P Switching + P Short-Circuit + P leakage (2. ) Dynamic power dissipation is a major source of leakage power, that is directly proportional to the number of signal transitions (0 -1 and 1 -0) in a digital circuit [4]. Signal transitions are of two types: functional transition and a glitch.…”

“…Signal transitions are of two types: functional transition and a glitch. According to reference [4] glitch power dissipation is 20 % to 70 % of total power dissipation. By varying gate delays and path delays in the circuit glitches can be reduced to some extent.…”

Glitch Analysis and Reduction in Combinational Circuits

“…As they dissipate 20-70% of total power dissipation, glitch is needed to be eliminated for low power design. P Total =P Static +P dynamic (1) P Total =P Switching +P Short-Circuit + P leakage (2) Total Power dissipation consists of mainly dynamic power dissipation and static power dissipation, further these are divided into switching power dissipation, leakage power dissipation, short circuit power dissipation. Dynamic power dissipation is a major source of leakage power, which is directly proportional to the number of signal transitions(1-0 and 0-1) in a digital circuit.…”